Scheda TecnicaSommarioMCP9800/1/2/3 Rev. A Silicon/Data Sheet Errata11. Module: Device Internal Latch-up at Higher Temperatures12. Module: POR Active During Oneshot Mode1Clarification/Corrections to the Data Sheet:1Appendix A: Revision History2Worldwide Sales and Service4Dimensioni: 62,8 KBPagine: 4Language: EnglishApri il manuale
Scheda TecnicaSommarioMCP9800/1/2/3, 2-Wire High-Accuracy Temperature Sensor Data Sheet11.0 Electrical Characteristics3DC Characteristics3Digital Input/Output Pin Characteristics4Temperature Characteristics4Serial Interface Timing Specifications52.0 Typical Performance Curves7FIGURE 2-1: Average Temperature Accuracy vs. Ambient Temperature, VDD = 3.3V.7FIGURE 2-2: Average Temperature Accuracy vs. Ambient Temperature.7FIGURE 2-3: Average Temperature Accuracy vs. Ambient Temperature, VDD = 3.3V.7FIGURE 2-4: Temperature Accuracy Histogram, TA = +25°C.7FIGURE 2-5: Supply Current vs. Ambient Temperature.7FIGURE 2-6: Shutdown Current vs. Ambient Temperature.7FIGURE 2-7: ALERT and SDA IOL vs. Ambient Temperature.8FIGURE 2-8: ALERT and SDA Output VOL vs. Ambient Temperature.8FIGURE 2-9: MCP980X Thermal Response vs Time.83.0 Pin Description9TABLE 3-1: Pin Function Table93.1 Serial Data Pin (SDA)93.2 Serial Clock Pin (SCLK)93.3 Power Supply Input (VDD)93.4 Ground (GND)93.5 ALERT Output93.6 Address Pins (A2, A1, A0)9TABLE 3-2: Slave Address94.0 Serial Communication114.1 2-Wire SMBus/Standard Mode I2C™ Protocol-Compatible Interface11TABLE 4-1: MCP9800 Serial Bus Protocol Descriptions114.1.1 Data Transfer114.1.2 Master/slave114.1.3 Start/Stop Condition114.1.4 Address Byte11FIGURE 4-1: Device Addressing.124.1.5 Data Valid124.1.6 Acknowledge (ACK)125.0 Functional Description13FIGURE 5-1: Functional Block Diagram.135.1 Temperature Sensor135.2 SD Analog-to-Digital Converter135.3 Registers14FIGURE 5-2: Register Block Diagram.14Register 5-1: Register Pointer14TABLE 5-1: Bit Assignment Summary for All Registers155.3.1 Ambient Temperature Register (TA)16Register 5-2: Ambient Temperature REgister (Ta) – Address <0000 0000>b16FIGURE 5-3: Timing Diagram for Reading +25.25°C Temperature from the TA Register (See Section 5.3.1 “Ambient Temperature Register (TA)”).175.3.2 Sensor Configuration Register (CONFIG)18Register 5-3: Configuration Register (CONFIG) – Address <0000 0001>b18FIGURE 5-4: Timing Diagram for Writing and Reading from the Configuration Register (See Section 5.3.2 “Sensor Configuration Register (CONFIG)”).195.3.3 Temperature Hysteresis Register (THYST)20Register 5-4: Temperature Hysteresis REgister (Thyst) – Address <0000 0010>b20FIGURE 5-5: Timing Diagram for Writing and Reading from the Temperature Hysteresis Register (See Section 5.3.3 “Temperature Hysteresis Register (THYST)”).215.3.4 Temperature Limit-Set Register (TSET)22Register 5-5: Temperature Limit-Set REgister (Tset) – Address <0000 0011>b22FIGURE 5-6: Timing Diagram for Writing and Reading from the Temperature Limit-set Register (See Section 5.3.4 “Temperature Limit-Set Register (TSET)”).235.3.4.1 Shutdown Mode245.3.4.2 One-Shot Mode24TABLE 5-2: Shutdown and One-shot Mode Description245.3.4.3 ALERT Output Configuration245.3.4.4 Comparator Mode245.3.4.5 Interrupt Mode24FIGURE 5-7: Alert Output.245.3.4.6 Fault Queue255.3.4.7 SD ADC Resolution25TABLE 5-3: Resolution and Conversion Time255.4 Summary of Power-up Condition25TABLE 5-4: Power-up defaults256.0 Applications Information276.1 Connecting to the Serial Bus27FIGURE 6-1: Pull-up Resistors on Serial Interface.276.2 Typical Application27FIGURE 6-2: Multiple Devices on I2C™ Bus.276.3 Layout Considerations27FIGURE 6-3: Power-supply Filter Using a Single Resistor.276.4 Thermal Considerations277.0 Packaging Information297.1 Package Marking Information29Appendix A: REVISION HISTORY37Product Identification System39Worldwide Sales and Service42Dimensioni: 755 KBPagine: 42Language: EnglishApri il manuale
Scheda TecnicaSommario1.0 Electrical Characteristics21.1 Maximum Ratings*2Figure 1-1: MCP100/101 Timing Diagram32.0 Applications Information42.1 The Need for Supervisory Circuits4Figure 2-1: Typical Application42.2 Negative Going Vdd Transients4Figure 2-2: Typical Transient Response42.3 Effect of Temperature on Timeout Period (trpu)5Figure 2-3: Typical trpu vs. Temperature5Figure 2-4: Idd vs. Temperature5Figure 2-5: Normalized Vtrip vs. Temperature5Figure 2-6: Vol vs. Iol5Figure 2-7: Normalized Iol vs. Temperature6Figure 2-8: Vdd - Voh vs. Ioh6Figure 2-9: Normalized Voh vs. Temperature63.0 packaging information73.1 Package Marking Information73.2 Package Detail Information8Dimensioni: 293 KBPagine: 16Apri il manuale
Scheda TecnicaSommario24AA16/24LC16B1Device Selection Table1Features:1Description:1Block Diagram1Note 1: Pins A0, A1 and A2 are not used by the 24XX16 (no internal connections).12: Available in I-temp, “AA” only.11.0 Electrical Characteristics2Absolute Maximum Ratings (†)2TABLE 1-1: DC Characteristics2TABLE 1-2: AC Characteristics3FIGURE 1-1: Bus Timing Data4FIGURE 1-2: Bus Timing Start/Stop42.0 Pin Descriptions5TABLE 2-1: Pin Function Table52.1 Serial Address/Data Input/Output (SDA)52.2 Serial Clock (SCL)52.3 Write-Protect (WP)52.4 A0, A1, A253.0 Functional Description64.0 Bus Characteristics64.1 Bus Not Busy (A)64.2 Start Data Transfer (B)64.3 Stop Data Transfer (C)64.4 Data Valid (D)64.5 Acknowledge6FIGURE 4-1: Data Transfer Sequence on the Serial Bus65.0 Device Addressing7FIGURE 5-1: Control Byte Allocation7FIGURE 5-2: Address Sequence Bit Assignments76.0 Write Operation86.1 Byte Write86.2 Page Write86.3 Write Protection8FIGURE 6-1: Byte Write8FIGURE 6-2: Page Write97.0 Acknowledge Polling10FIGURE 7-1: Acknowledge Polling Flow108.0 Read Operation118.1 Current Address Read118.2 Random Read118.3 Sequential Read118.4 Noise Protection11FIGURE 8-1: Current Address Read11FIGURE 8-2: Random Read12FIGURE 8-3: Sequential Read129.0 Packaging Information139.1 Package Marking Information13Appendix A: REVISION HISTORY34The Microchip Web Site35Customer Change Notification Service35Customer Support35Reader Response36Product Identification System37Trademarks39Worldwide Sales40Dimensioni: 1,15 MBPagine: 40Language: EnglishApri il manuale
Scheda TecnicaSommarioDevices Included In This Data Sheet:3High-Performance RISC CPU:3Special Microcontroller Features:3Low-Power Features/CMOS Technology:3Peripheral Features (PIC10F200/202):3Peripheral Features (PIC10F204/206):3TABLE 1-1: PIC10F20X Memory and Features3SOT-23 Pin Diagrams48-Pin PDIP Pin Diagrams48-Pin DFN Pin Diagrams4Table of Contents5Most Current Data Sheet5Errata5Customer Notification System51.0 General Description71.1 Applications7TABLE 1-1: PIC10F200/202/204/206 Devices72.0 PIC10F200/202/204/206 Device Varieties92.1 Quick Turn Programming (QTP) Devices92.2 Serialized Quick Turn ProgrammingSM (SQTPSM) Devices93.0 Architectural Overview11TABLE 3-1: PIC10F2XX Memory11FIGURE 3-1: PIC10F200/202 Block Diagram12FIGURE 3-2: PIC10F204/206 Block Diagram13TABLE 3-2: PIC10F200/202/204/206 Pinout Description143.1 Clocking Scheme/Instruction Cycle153.2 Instruction Flow/Pipelining15FIGURE 3-3: Clock/Instruction Cycle15EXAMPLE 3-1: Instruction Pipeline Flow154.0 Memory Organization174.1 Program Memory Organization for the PIC10F200/20417FIGURE 4-1: Program Memory Map and Stack for the PIC10F200/204174.2 Program Memory Organization for the PIC10F202/20618FIGURE 4-2: Program Memory Map and Stack for the PIC10F202/206184.3 Data Memory Organization184.3.1 General Purpose Register File18FIGURE 4-3: PIC10F200/204 Register File Map19FIGURE 4-4: PIC10F202/206 Register File Map194.3.2 Special Function Registers20TABLE 4-1: Special Function Register (SFR) Summary (PIC10F200/202/204/206)204.4 STATUS Register21Register 4-1: STATUS Register214.5 OPTION Register22Register 4-2: OPTION Register224.6 OSCCAL Register23Register 4-3: OSCCAL Register234.7 Program Counter24FIGURE 4-5: Loading of PC Branch Instructions244.7.1 Effects Of Reset244.8 Stack244.9 Indirect Data Addressing: INDF and FSR Registers254.10 Indirect Addressing25EXAMPLE 4-1: How to Clear RAM Using Indirect Addressing25FIGURE 4-6: Direct/Indirect Addressing (PIC10F200/202/204/206)255.0 I/O Port275.1 GPIO275.2 TRIS Registers27TABLE 5-1: Order of Precedence for Pin Functions275.3 I/O Interfacing27FIGURE 5-1: PIC10F200/202/204/206 Equivalent Circuit for a Single I/O Pin27TABLE 5-2: Summary of Port Registers285.4 I/O Programming Considerations285.4.1 Bidirectional I/O Ports28EXAMPLE 5-1: Read-modify-write Instructions on an I/O Port285.4.2 Successive Operations on I/O Ports28FIGURE 5-2: Successive I/O Operation (PIC10F200/202/204/206)296.0 Timer0 Module and TMR0 Register (PIC10F200/202)31FIGURE 6-1: TIMER0 Block Diagram31FIGURE 6-2: TIMER0 Timing: Internal Clock/No Prescale31FIGURE 6-3: TIMER0 Timing: Internal Clock/Prescale 1:232TABLE 6-1: Registers Associated with TIMER0326.1 Using Timer0 with an External Clock (PIC10F200/202)326.1.1 External Clock Synchronization326.1.2 TIMER0 Increment Delay33FIGURE 6-4: TIMER0 Timing with External Clock336.2 Prescaler336.2.1 Switching Prescaler Assignment33EXAMPLE 6-1: Changing Prescaler (TIMER0 ® WDT)33EXAMPLE 6-2: Changing Prescaler (WDT®TIMER0)34FIGURE 6-5: Block Diagram of the TIMER0/WDT Prescaler347.0 Timer0 Module and TMR0 Register (PIC10F204/206)35FIGURE 7-1: TIMER0 Block Diagram (PIC10F204/206)35FIGURE 7-2: TIMER0 Timing: Internal Clock/No Prescale36FIGURE 7-3: TIMER0 Timing: Internal Clock/Prescale 1:236TABLE 7-1: Registers Associated with Timer0367.1 Using Timer0 with an External Clock (PIC10F204/206)367.1.1 External Clock Synchronization367.1.2 TIMER0 Increment Delay37FIGURE 7-4: TIMER0 Timing with External Clock377.2 Prescaler377.2.1 Switching Prescaler Assignment37EXAMPLE 7-1: Changing Prescaler (TIMER0 ® WDT)37EXAMPLE 7-2: Changing Prescaler (WDT®TIMER0)38FIGURE 7-5: Block Diagram of the TIMER0/WDT Prescaler388.0 Comparator Module39Register 8-1: CMCON0 Register398.1 Comparator Configuration40FIGURE 8-1: Block Diagram of the Comparator40TABLE 8-1: TMR0 Clock Source Function Muxing408.2 Comparator Operation41FIGURE 8-2: Single Comparator418.3 Comparator Reference418.4 Comparator Response Time418.5 Comparator Output418.6 Comparator Wake-up Flag418.7 Comparator Operation During Sleep418.8 Effects of a Reset418.9 Analog Input Connection Considerations41FIGURE 8-3: Analog Input Mode42TABLE 8-2: Registers Associated with Comparator Module429.0 Special Features of the CPU439.1 Configuration Bits43Register 9-1: CONFIGURATION Word for PIC10F200/202/204/206(1), (2)439.2 Oscillator Configurations449.2.1 Oscillator Types449.2.2 Internal 4 MHz Oscillator449.3 Reset44TABLE 9-1: Reset Conditions for Registers – PIC10F200/202/204/20644TABLE 9-2: Reset Condition for Special Registers459.3.1 MCLR Enable45FIGURE 9-1: MCLR Select459.4 Power-on Reset (POR)45FIGURE 9-2: Simplified Block Diagram of On-chip Reset Circuit46FIGURE 9-3: Time-out Sequence on Power-up (MCLR Pulled Low)46FIGURE 9-4: Time-out Sequence on Power-up (MCLR Tied To Vdd): Fast Vdd Rise Time46FIGURE 9-5: Time-Out Sequence on Power-Up (MCLR Tied to Vdd): Slow Vdd Rise Time479.5 Device Reset Timer (DRT)48TABLE 9-3: DRT (Device Reset Timer Period)489.6 Watchdog Timer (WDT)489.6.1 WDT Period489.6.2 WDT Programming Considerations48FIGURE 9-6: Watchdog Timer Block Diagram49TABLE 9-4: Summary of Registers Associated with the Watchdog Timer499.7 Time-out Sequence, Power-down and Wake-up from Sleep Status Bits (TO, PD, GPWUF, CWUF)50TABLE 9-5: TO, PD, GPWUF, CWUF Status After Reset509.8 Reset on Brown-out50FIGURE 9-7: Brown-out Protection Circuit 150FIGURE 9-8: Brown-out Protection Circuit 250FIGURE 9-9: Brown-out Protection Circuit 3519.9 Power-Down Mode (Sleep)519.9.1 Sleep519.9.2 Wake-up from Sleep519.10 Program Verification/Code Protection529.11 ID Locations529.12 In-Circuit Serial Programming™52FIGURE 9-10: Typical In-Circuit Serial Programming™ Connection5210.0 Instruction Set Summary53TABLE 10-1: Opcode Field Descriptions53FIGURE 10-1: General Format for Instructions53TABLE 10-2: Instruction Set Summary5411.0 Development Support6111.1 MPLAB X Integrated Development Environment Software6111.2 MPLAB XC Compilers6211.3 MPASM Assembler6211.4 MPLINK Object Linker/ MPLIB Object Librarian6211.5 MPLAB Assembler, Linker and Librarian for Various Device Families6211.6 MPLAB X SIM Software Simulator6311.7 MPLAB REAL ICE In-Circuit Emulator System6311.8 MPLAB ICD 3 In-Circuit Debugger System6311.9 PICkit 3 In-Circuit Debugger/ Programmer6311.10 MPLAB PM3 Device Programmer6311.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits6411.12 Third-Party Development Tools6412.0 Electrical Characteristics65Absolute Maximum Ratings(†)65FIGURE 12-1: PIC10F200/202/204/206 Voltage-Frequency Graph, -40°C £ ta £ +125°C6612.1 DC Characteristics: PIC10F200/202/204/206 (Industrial)6712.2 DC Characteristics: PIC10F200/202/204/206 (Extended)6812.3 DC Characteristics: PIC10F200/202/204/206 (Industrial, Extended)69TABLE 12-1: Comparator Specifications70TABLE 12-2: Pull-up Resistor Ranges7012.4 Timing Parameter Symbology and Load Conditions – PIC10F200/202/204/20671FIGURE 12-2: Load Conditions – PIC10F200/202/204/20671TABLE 12-3: Calibrated Internal RC Frequencies – PIC10F200/202/204/20672FIGURE 12-3: Reset, Watchdog Timer and Device Reset Timer Timing – PIC10F200/202/204/20672TABLE 12-4: Reset, Watchdog Timer and Device Reset Timer – PIC10F200/202/204/20673FIGURE 12-4: Timer0 Clock Timings – PIC10F200/202/204/20673TABLE 12-5: Timer0 Clock Requirements – PIC10F200/202/204/2067313.0 DC and AC Characteristics Graphs and Tables.75FIGURE 13-1: Idd vs. Vdd Over Fosc75FIGURE 13-2: Typical Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)76FIGURE 13-3: Maximum Ipd vs. Vdd (Sleep Mode, all Peripherals Disabled)76FIGURE 13-4: Comparator Ipd vs. Vdd (Comparator Enabled)77FIGURE 13-5: Typical WDT Ipd VS. Vdd77FIGURE 13-6: Maximum WDT Ipd VS. Vdd Over Temperature78FIGURE 13-7: WDT TIME-OUT VS. Vdd Over Temperature (No Prescaler)78FIGURE 13-8: Vol VS. Iol Over Temperature (Vdd = 3.0V)79FIGURE 13-9: Vol VS. Iol Over Temperature (Vdd = 5.0V)79FIGURE 13-10: Voh VS. Ioh Over Temperature (Vdd = 3.0V)80FIGURE 13-11: Voh VS. Ioh Over Temperature (Vdd = 5.0V)80FIGURE 13-12: TTL Input Threshold Vin VS. Vdd81FIGURE 13-13: Schmitt Trigger Input Threshold Vin VS. Vdd81FIGURE 13-14: INTOSC (Internal oscillator) powerup Times vs. Vdd8214.0 Packaging Information8314.1 Package Marking Information83TABLE 14-1: 8-Lead 2X3 dfn (mc) tOP mARKING84TABLE 14-2: 6-Lead SOT-23 (OT) Package tOP mARKING84Appendix A: Revision History91INDEX93The Microchip Web Site95Customer Change Notification Service95Customer Support95Product Identification System97Worldwide Sales98Dimensioni: 1,41 MBPagine: 98Language: EnglishApri il manuale
Manuale UtenteSommarioPreface5Chapter 1. Product Overview91.1 Introduction91.2 What is the MCP9800 Temperature Data Logger Demo Board 2?91.3 What does the MCP9800 Temperature Data Logger Demo Board 2 Kit Include?9Chapter 2. Installation and Operation112.1 Introduction112.2 Features112.3 Getting Started11Figure 1-1: MCP9800 Temperature Data Logger Demo Board 2 Functional Block Diagram12Figure 1-2: PICkit™ 2 Programmer GUI Window on the PC13Figure 1-3: SEEVAL® 32 Evaluation Tool GUI Window on the PC142.4 Functional Description152.5 I2C™ Subroutines15Appendix A. Schematic and Bill of Materials (BOM)19Figure 1-1: MCP9800 Temp Sensor SEEVAL® 32 Data Logger Schematic19Figure 1-2: MCP9800 Temp Sensor SEEVAL® 32 Data Logger BOM20Figure 1-3: MCP9800 Temp Sensor SEEVAL® 32 Data Logger BOM (Continued)21Worldwide Sales and Service22Dimensioni: 351 KBPagine: 22Language: EnglishApri il manuale
