Manuali utente per NEC uPD78P078

Sommario

• COVER

  1
• Major Revisions in This Edition

  6
• INTRODUCTION

  7
• CHAPTER 1 OUTLINE (uPD78078 SUBSERIES)

  33
  • 1.1 Features

    33
  • 1.2 Application Fields

    34
  • 1.3 Ordering Information

    34
  • 1.4 Quality Grade

    35
  • 1.5 Pin Configuration (Top View)

    36
  • 1.6 78K/0 Series Expansion

    42
  • 1.7 Block Diagram

    44
  • 1.8 Outline of Function

    45
  • 1.9 Mask Options

    47
  • 1.10 Differences with uPD78054 Subseries

    47
• CHAPTER 2 OUTLINE (uPD78078Y SUBSERIES)

  49
  • 2.1 Features

    49
  • 2.2 Application Fields

    50
  • 2.3 Ordering Information

    50
  • 2.4 Quality Grade

    51
  • 2.5 Pin Configuration (Top View)

    52
  • 2.6 78K/0 Series Expansion

    58
  • 2.7 Block Diagram

    60
  • 2.8 Outline of Function

    61
  • 2.9 Mask Options

    63
  • 2.10 Differences with uPD78054Y Subseries

    63
• CHAPTER 3 PIN FUNCTION (uPD78078 SUBSERIES)

  65
  • 3.1 Pin Function List

    65
    • 3.1.1 Normal operating mode pins

      65
    • 3.1.2 PROM programming mode pins (uPD78P078 only)

      69
  • 3.2 Description of Pin Functions

    70
    • 3.2.1 P00 to P07 (Port 0)

      70
    • 3.2.2 P10 to P17 (Port 1)

      70
    • 3.2.3 P20 to P27 (Port 2)

      71
    • 3.2.4 P30 to P37 (Port 3)

      72
    • 3.2.5 P40 to P47 (Port 4)

      72
    • 3.2.6 P50 to P57 (Port 5)

      73
    • 3.2.7 P60 to P67 (Port 6)

      73
    • 3.2.8 P70 to P72 (Port 7)

      74
    • 3.2.9 P80 to P87 (Port 8)

      74
    • 3.2.10 P90 to P96 (Port 9)

      75
    • 3.2.11 P100 to P103 (Port 10)

      75
    • 3.2.12 P120 to P127 (Port 12)

      75
    • 3.2.13 P130 and P131 (Port 13)

      76
    • 3.2.14 AVREF0

      76
    • 3.2.15 AVREF1

      76
    • 3.2.16 AVDD

      76
    • 3.2.17 AVSS

      76
    • 3.2.18 RESET#

      76
    • 3.2.19 X1 and X2

      76
    • 3.2.20 XT1 and XT2

      76
    • 3.2.21 VDD

      77
    • 3.2.22 VSS

      77
    • 3.2.23 VPP (uPD78P078 only)

      77
    • 3.2.24 IC (Mask ROM version only)

      77
  • 3.3 Input/output Circuits and Recommended Connection of Unused Pins

    78
• CHAPTER 4 PIN FUNCTION (uPD78078Y SUBSERIES)

  83
  • 4.1 Pin Function List

    83
    • 4.1.1 Normal operating mode pins

      83
    • 4.1.2 PROM programming mode pins (uPD78P078Y only)

      87
  • 4.2 Description of Pin Functions

    88
    • 4.2.1 P00 to P07 (Port 0)

      88
    • 4.2.2 P10 to P17 (Port 1)

      88
    • 4.2.3 P20 to P27 (Port 2)

      89
    • 4.2.4 P30 to P37 (Port 3)

      90
    • 4.2.5 P40 to P47 (Port 4)

      90
    • 4.2.6 P50 to P57 (Port 5)

      91
    • 4.2.7 P60 to P67 (Port 6)

      91
    • 4.2.8 P70 to P72 (Port 7)

      92
    • 4.2.9 P80 to P87 (Port 8)

      92
    • 4.2.10 P90 to P96 (Port 9)

      93
    • 4.2.11 P100 to P103 (Port 10)

      93
    • 4.2.12 P120 to P127 (Port 12)

      93
    • 4.2.13 P130 and P131 (Port 13)

      94
    • 4.2.14 AVREF0

      94
    • 4.2.15 AVREF1

      94
    • 4.2.16 AVDD

      94
    • 4.2.17 AVSS

      94
    • 4.2.18 RESET#

      94
    • 4.2.19 X1 and X2

      94
    • 4.2.20 XT1 and XT2

      94
    • 4.2.21 VDD

      95
    • 4.2.22 VSS

      95
    • 4.2.23 VPP (uPD78P078Y only)

      95
    • 4.2.24 IC (Mask ROM version only)

      95
  • 4.3 Input/output Circuits and Recommended Connection of Unused Pins

    96
• CHAPTER 5 CPU ARCHITECTURE

  101
  • 5.1 Memory Spaces

    101
    • 5.1.1 Internal program memory space

      104
    • 5.1.2 Internal data memory space

      106
    • 5.1.3 Special function register (SFR) area

      106
    • 5.1.4 External memory space

      106
    • 5.1.5 Data memory addressing

      107
  • 5.2 Processor Registers

    110
    • 5.2.1 Control registers

      110
    • 5.2.2 General registers

      113
    • 5.2.3 Special function register (SFR)

      114
  • 5.3 Instruction Address Addressing

    118
    • 5.3.1 Relative addressing

      118
    • 5.3.2 Immediate addressing

      119
    • 5.3.3 Table indirect addressing

      120
    • 5.3.4 Register addressing

      121
  • 5.4 Operand Address Addressing

    122
    • 5.4.1 Implied addressing

      122
    • 5.4.2 Register addressing

      123
    • 5.4.3 Direct addressing

      124
    • 5.4.4 Short direct addressing

      125
    • 5.4.5 Special function register (SFR) addressing

      126
    • 5.4.6 Register indirect addressing

      127
    • 5.4.7 Based addressing

      128
    • 5.4.8 Based indexed addressing

      129
    • 5.4.9 Stack addressing

      129
• CHAPTER 6 PORT FUNCTIONS

  131
  • 6.1 Port Functions

    131
  • 6.2 Port Configuration

    136
    • 6.2.1 Port 0

      136
    • 6.2.2 Port 1

      138
    • 6.2.3 Port 2 (uPD78078 Subseries)

      139
    • 6.2.4 Port 2 (uPD78078Y Subseries)

      141
    • 6.2.5 Port 3

      143
    • 6.2.6 Port 4

      144
    • 6.2.7 Port 5

      145
    • 6.2.8 Port 6

      146
    • 6.2.9 Port 7

      148
    • 6.2.10 Port 8

      150
    • 6.2.11 Port 9

      151
    • 6.2.12 Port 10

      153
    • 6.2.13 Port 12

      155
    • 6.2.14 Port 13

      156
  • 6.3 Port Function Control Registers

    157
  • 6.4 Port Function Operations

    163
    • 6.4.1 Writing to input/output port

      163
    • 6.4.2 Reading from input/output port

      163
    • 6.4.3 Operations on input/output port

      163
  • 6.5 Selection of Mask Option

    164
• CHAPTER 7 CLOCK GENERATOR

  165
  • 7.1 Clock Generator Functions

    165
  • 7.2 Clock Generator Configuration

    166
  • 7.3 Clock Generator Control Register

    167
  • 7.4 System Clock Oscillator

    171
    • 7.4.1 Main system clock oscillator

      171
    • 7.4.2 Subsystem clock oscillator

      172
    • 7.4.3 Divider

      174
    • 7.4.4 When no subsystem clocks are used

      174
  • 7.5 Clock Generator Operations

    175
    • 7.5.1 Main system clock operations

      176
    • 7.5.2 Subsystem clock operations

      177
  • 7.6 Changing System Clock and CPU Clock Settings

    178
    • 7.6.1 Time required for switchover between system clock and CPU clock

      178
    • 7.6.2 System clock and CPU clock switching procedure

      179
• CHAPTER 8 16-BIT TIMER/EVENT COUNTER

  181
  • 8.1 Outline of Timers Incorporated into uPD78078, 78078Y Subseries

    181
  • 8.2 16-Bit Timer/Event Counter Functions

    183
  • 8.3 16-Bit Timer/Event Counter Configuration

    185
  • 8.4 16-Bit Timer/Event Counter Control Registers

    190
  • 8.5 16-Bit Timer/Event Counter Operations

    198
    • 8.5.1 Interval timer operations

      198
    • 8.5.2 PWM output operations

      200
    • 8.5.3 PPG output operations

      203
    • 8.5.4 Pulse width measurement operations

      204
    • 8.5.5 External event counter operation

      211
    • 8.5.6 Square-wave output operation

      213
    • 8.5.7 One-shot pulse output operation

      215
  • 8.6 16-Bit Timer/Event Counter Operating Precautions

    219
• CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2

  223
  • 9.1 8-Bit Timer/Event Counters 1 and 2 Functions

    223
    • 9.1.1 8-bit timer/event counter mode

      223
    • 9.1.2 16-bit timer/event counter mode

      226
  • 9.2 8-Bit Timer/Event Counters 1 and 2 Configurations

    228
  • 9.3 8-Bit Timer/Event Counters 1 and 2 Control Registers

    231
  • 9.4 8-Bit Timer/Event Counters 1 and 2 Operations

    236
    • 9.4.1 8-bit timer/event counter mode

      236
    • 9.4.2 16-bit timer/event counter mode

      242
  • 9.5 8-Bit Timer/Event Counters 1 and 2 Precautions

    246
• CHAPTER 10 8-BIT TIMER/EVENT COUNTERS 5 AND 6

  249
  • 10.1 8-Bit Timer/Event Counters 5 and 6 Functions

    249
  • 10.2 8-Bit Timer/Event Counters 5 and 6 Configurations

    252
  • 10.3 8-Bit Timer/Event Counters 5 and 6 Control Registers

    254
  • 10.4 8-Bit Timer/Event Counters 5 and 6 Operations

    259
    • 10.4.1 Interval timer operations

      259
    • 10.4.2 External event counter operation

      261
    • 10.4.3 Square-wave output

      262
    • 10.4.4 PWM output operations

      264
  • 10.5 8-Bit Timer/Event Counters 5 and 6 Precautions

    267
• CHAPTER 11 WATCH TIMER

  269
  • 11.1 Watch Timer Functions

    269
  • 11.2 Watch Timer Configuration

    270
  • 11.3 Watch Timer Control Registers

    271
  • 11.4 Watch Timer Operations

    274
    • 11.4.1 Watch timer operation

      274
    • 11.4.2 Interval timer operation

      274
• CHAPTER 12 WATCHDOG TIMER

  275
  • 12.1 Watchdog Timer Functions

    275
  • 12.2 Watchdog Timer Configuration

    277
  • 12.3 Watchdog Timer Control Registers

    278
  • 12.4 Watchdog Timer Operations

    281
    • 12.4.1 Watchdog timer operation

      281
    • 12.4.2 Interval timer operation

      282
• CHAPTER 13 CLOCK OUTPUT CONTROL CIRCUIT

  283
  • 13.1 Clock Output Control Circuit Functions

    283
  • 13.2 Clock Output Control Circuit Configuration

    284
  • 13.3 Clock Output Function Control Registers

    285
• CHAPTER 14 BUZZER OUTPUT CONTROL CIRCUIT

  289
  • 14.1 Buzzer Output Control Circuit Functions

    289
  • 14.2 Buzzer Output Control Circuit Configuration

    289
  • 14.3 Buzzer Output Function Control Registers

    290
• CHAPTER 15 A/D CONVERTER

  293
  • 15.1 A/D Converter Functions

    293
  • 15.2 A/D Converter Configuration

    293
  • 15.3 A/D Converter Control Registers

    296
  • 15.4 A/D Converter Operations

    300
    • 15.4.1 Basic operations of A/D converter

      300
    • 15.4.2 Input voltage and conversion results

      302
    • 15.4.3 A/D converter operating mode

      303
  • 15.5 A/D Converter Cautions

    305
• CHAPTER 16 D/A CONVERTER

  309
  • 16.1 D/A Converter Functions

    309
  • 16.2 D/A Converter Configuration

    310
  • 16.3 D/A Converter Control Registers

    312
  • 16.4 D/A Converter Operations

    313
  • 16.5 D/A Converter Cautions

    314
• CHAPTER 17 SERIAL INTERFACE CHANNEL 0 (uPD78078 SUBSERIES)

  315
  • 17.1 Serial Interface Channel 0 Functions

    316
  • 17.2 Serial Interface Channel 0 Configuration

    318
  • 17.3 Serial Interface Channel 0 Control Registers

    321
  • 17.4 Serial Interface Channel 0 Operations

    328
    • 17.4.1 Operation stop mode

      328
    • 17.4.2 3-wire serial I/O mode operation

      329
    • 17.4.3 SBI mode operation

      333
    • 17.4.4 2-wire serial I/O mode operation

      357
    • 17.4.5 SCK0#/P27 pin output manipulation

      363
• CHAPTER 18 SERIAL INTERFACE CHANNEL 0 (uPD78078Y Subseries)

  365
  • 18.1 Serial Interface Channel 0 Functions

    366
  • 18.2 Serial Interface Channel 0 Configuration

    368
  • 18.3 Serial Interface Channel 0 Control Registers

    372
  • 18.4 Serial Interface Channel 0 Operations

    380
    • 18.4.1 Operation stop mode

      380
    • 18.4.2 3-wire serial I/O mode operation

      381
    • 18.4.3 2-wire serial I/O mode operation

      385
    • 18.4.4 I2C bus mode operation

      390
    • 18.4.5 Cautions on use of I2C bus mode

      408
    • 18.4.6 Restrictions in I2C bus mode

      411
    • 18.4.7 SCK0#/SCL/P27 pin output manipulation

      413
• CHAPTER 19 SERIAL INTERFACE CHANNEL 1

  415
  • 19.1 Serial Interface Channel 1 Functions

    415
  • 19.2 Serial Interface Channel 1 Configuration

    416
  • 19.3 Serial Interface Channel 1 Control Registers

    418
  • 19.4 Serial Interface Channel 1 Operations

    425
    • 19.4.1 Operation stop mode

      425
    • 19.4.2 3-wire serial I/O mode operation

      426
    • 19.4.3 3-wire serial I/O mode operation with automatic transmit/receive function

      429
• CHAPTER 20 SERIAL INTERFACE CHANNEL 2

  457
  • 20.1 Serial Interface Channel 2 Functions

    457
  • 20.2 Serial Interface Channel 2 Configuration

    458
  • 20.3 Serial Interface Channel 2 Control Registers

    461
  • 20.4 Serial Interface Channel 2 Operation

    469
    • 20.4.1 Operation stop mode

      469
    • 20.4.2 Asynchronous serial interface (UART) mode

      471
    • 20.4.3 3-wire serial I/O mode

      484
    • 20.4.4 Restrictions on using UART mode

      491
• CHAPTER 21 REAL-TIME OUTPUT PORT

  495
  • 21.1 Real-Time Output Port Functions

    495
  • 21.2 Real-Time Output Port Configuration

    495
  • 21.3 Real-Time Output Port Control Registers

    497
• CHAPTER 22 INTERRUPT FUNCTIONS

  499
  • 22.1 Interrupt Function Types

    499
  • 22.2 Interrupt Sources and Configuration

    500
  • 22.3 Interrupt Function Control Registers

    504
  • 22.4 Interrupt Servicing Operations

    513
    • 22.4.1 Non-maskable interrupt request acknowledge operation

      513
    • 22.4.2 Maskable interrupt request acknowledge operation

      516
    • 22.4.3 Software interrupt request acknowledge operation

      518
    • 22.4.4 Multiple interrupt servicing

      519
    • 22.4.5 Interrupt request reserve

      522
  • 22.5 Test Functions

    523
    • 22.5.1 Registers controlling the test function

      523
    • 22.5.2 Test input signal acknowledge operation

      525
• CHAPTER 23 EXTERNAL DEVICE EXPANSION FUNCTION

  527
  • 23.1 External Device Expansion Functions

    527
  • 23.2 External Device Expansion Function Control Register

    531
  • 23.3 External Device Expansion Function Timing

    534
    • 23.3.1 Timings in multiplexed bus mode

      534
    • 23.3.2 Timings in separate bus mode

      539
• CHAPTER 24 STANDBY FUNCTION

  545
  • 24.1 Standby Function and Configuration

    545
    • 24.1.1 Standby function

      545
    • 24.1.2 Standby function control register

      546
  • 24.2 Standby Function Operations

    547
    • 24.2.1 HALT mode

      547
    • 24.2.2 STOP mode

      550
• CHAPTER 25 RESET FUNCTION

  553
  • 25.1 Reset Function

    553
• CHAPTER 26 ROM CORRECTION

  559
  • 26.1 ROM Correction Functions

    559
  • 26.2 ROM Correction Configuration

    559
  • 26.3 ROM Correction Control Registers

    561
  • 26.4 ROM Correction Application

    562
  • 26.5 ROM Correction Example

    565
  • 26.6 Program Execution Flow

    566
  • 26.7 Cautions on ROM Correction

    568
• CHAPTER 27 uPD78P078, 78P078Y

  569
  • 27.1 Internal Memory Size Switching Register

    570
  • 27.2 Internal Extension RAM Size Switching Register

    571
  • 27.3 PROM Programming

    572
    • 27.3.1 Operating modes

      572
    • 27.3.2 PROM write procedure

      574
    • 27.3.3 PROM reading procedure

      578
  • 27.4 Erasure Procedure (uPD78P078KL-T and 78P078YKL-T Only)

    579
  • 27.5 Opaque Film Masking Window (uPD78P078KL-T and 78P078YKL-T Only)

    579
  • 27.6 Screening of One-Time PROM Versions

    579
• CHAPTER 28 INSTRUCTION SET

  581
  • 28.1 Legends Used in Operation List

    582
    • 28.1.1 Operand identifiers and description

      582
    • 28.1.2 Description of "operation" column

      583
    • 23.1.3 Description of "flag operation" column

      583
  • 28.2 Operation List

    584
  • 28.3 Instructions Listed by Addressing Type

    592
• APPENDIX A DIFFERENCES BETWEEN uPD78078, 78075B SUBSERIES, AND uPD78070A

  597
• APPENDIX B DEVELOPMENT TOOLS

  599
  • B.1 Language Processing Software

    602
  • B.2 PROM Writing Tools

    604
    • B.2.1 Hardware

      604
    • B.2.2 Software

      604
  • B.3 Debugging Tools

    605
    • B.3.1 Hardware

      605
    • B.3.2 Software

      607
  • B.4 OS for IBM PC

    609
  • B.5 System Upgrading from Former-type In-circuit Emulator for 78K/0 Series to IE-78001-R-A

    609
• APPENDIX C EMBEDDED SOFTWARE

  613
• APPENDIX D REGISTER INDEX

  615
  • D.1 Register Name Index

    615
  • D.2 Register Symbol Index

    619
• APPENDIX E REVISION HISTORY

  623