Manuale UtenteSommarioCover1Special Attention and Precautions3Chapter Door5Contents9List of Figures & Tables16List of Figures16List of Tables23Chapter 1 General Specifications271.1 Overview281.2 Features281.3 Block Diagram301.4 Pin Description311.4.1 Pin Assignments311.4.2 Pin Functions33Chapter 2 CPU352.1 Basic Specifications of CPU362.2 Block Diagram372.3 Programming Model382.3.1 CPU Registers382.3.2 Control Registers412.4 Instructions442.4.1 Addressing Modes442.4.2 Data Types452.4.3 Instruction Set462.5 Interrupts482.5.1 Overview of Interrupts482.5.2 Registers492.5.3 Interrupt Types522.5.4 Interrupt Definition53Chapter 3 Extension Instruction Specifications573.1 Operation Extension Function583.2 Extension Instructions593.2.1 Explanation of Notations593.2.2 Extension Block Register Set603.2.3 Extension Instruction Details613.2.4 Programming Notes87Chapter 4 Memory Modes974.1 Memory Mode Types and Selection984.2 Memory Mode Pin Processing994.3 Description of Memory Mode1004.3.1 Memory Extension Mode1004.3.2 Processor Mode101Chapter 5 Operating Mode1035.1 Overview1045.2 Reset Mode1055.3 Low Power Mode106Chapter 6 Clock Generator1076.1 Overview1086.2 Features1086.3 Block Diagram1086.4 Description of Operation1096.4.1 Input Frequency Setting1096.4.2 Internal Clock Supply109Chapter 7 Internal Memory1117.1 Overview1127.2 Features1127.3 Internal Memory Configuration113Chapter 8 Bus Controller (BC)1158.1 Overview1168.2 Features1168.3 Bus Configuration1178.4 Block Diagram1178.5 Pin Functions1198.6 Description of Registers1218.6.1 Memory Block 0 Control Register1228.6.2 Memory Block 1 Control Register1248.6.3 Memory Block 2 Control Register1288.6.4 Memory Block 3 Control Register1338.6.5 DRAM control register1368.6.6 Refresh count register1378.6.7 Page Row Address Register1388.6.8 Clock Control Register1388.7 Space Partitioning1408.8 Operation Clocks1428.9 Mode Settings1428.10 Bus Cycle1438.11 Store Buffer1448.12 Accessing the Internal I/O Space1458.13 External Memory Space Access (Non-DRAM Spaces)1468.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode1478.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode1498.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode1518.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode1538.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode1558.13.6 8-bit Bus in Asynchronous Mode and in Address/Data Separate Mode1598.13.7 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode1608.13.8 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode1628.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode1658.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode1668.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode1708.13.12 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode1748.14 External Memory Space Access (DRAM Space)1768.14.1 DRAM Space1768.14.2 DRAM page mode1798.14.3 Software Page Mode1808.14.4 DRAM refresh1828.15 Bus Arbitration1848.16 Cautions187Chapter 9 Interrupt Controller1899.1 Overview1909.2 Features1909.3 System Diagram1909.4 Block Diagram1919.5 Description of Registers1949.6 Description of Operation218Chapter 10 8-bit Timers22110.1 Overview22210.2 Features22210.3 Block Diagram22310.4 Functions22910.5 Description of Registers23010.6 Description of Operation24010.6.1 Interval Timers and Timer Output24010.6.2 Event Counting24410.6.3 Cascaded Connection24610.6.4 PWM Output251Chapter 11 16-bit Timers25511.1 Overview25611.2 Features25611.3 Block Diagram25711.4 Functions26111.5 Description of Registers26211.6 Description of Operation of Timer 1027211.6.1 Compare Register Settings27211.6.2 Capture Register Settings27311.6.3 Pin Output Settings27511.6.4 Starting by an External Trigger27811.6.5 One-shot Operation28011.6.6 Interval Timer28211.6.7 Event Counting28511.7 Description of Operation of Timers 11, 12, and 1328711.7.1 Interval Timer and Timer Output28711.7.2 Event Counting290Chapter 12 Watchdog Timer29312.1 Overview29412.2 Features29412.3 Block Diagram29512.4 Description of Registers29612.5 Description of Operation299Chapter 13 Serial Interface30313.1 Overview30413.2 General-purpose serial interface30513.2.1 Features30513.2.2 Block Diagram of General-Purpose Serial Interface30713.2.3 Description of Registers for the General-Purpose Serial Interface30813.2.4 Description of Operation31213.3 Clock Synchronous Serial Interface32613.3.1 Features32613.3.2 Block Diagram of Clock Synchronous Serial Interface32713.3.3 Description of Registers for the Clock Synchronous Serial Interface32813.3.4 Description of Operation33413.4 Universal Asynchronous Receiver-Transceiver Serial Interface33813.4.1 Features33813.4.2 Block Diagram of UART Serial Interface33913.4.3 Description of Registers for the UART Serial Interface34013.4.4 Description of Operation347Chapter 14 A/D Converter35514.1 Overview35614.2 Features35714.3 Block Diagram35814.4 Description of Registers35914.5 Description of Operation361Chapter 15 I/O Ports36715.1 Overview36815.2 Port 037215.2.1 Block Diagram37215.2.2 Register Descriptions37315.2.3 Pin Configurations37515.3 Port 137615.3.1 Block Diagram37615.3.2 Register Descriptions37815.3.3 Pin Configurations38015.4 Port 238115.4.1 Block Diagram38115.4.2 Register Descriptions38215.4.3 Pin Configurations38415.5 Port 338515.5.1 Block Diagram38515.5.2 Register Descriptions38615.5.3 Pin Configurations38715.6 Port 438815.6.1 Block Diagram38815.6.2 Register Descriptions39115.6.3 Pin Configurations39415.7 Port 539515.7.1 Block Diagram39515.7.2 Register Descriptions40015.7.3 Pin Configurations40315.8 Port 640415.8.1 Block Diagram40415.8.2 Register Descriptions40515.8.3 Pin Configurations40615.9 Port 740715.9.1 Block Diagram40715.9.2 Register Descriptions40815.9.3 Pin Configurations41015.10 Port 841115.10.1 Block Diagram41115.10.2 Register Descriptions41215.10.3 Pin Configurations41315.11 Port 941415.11.1 Block Diagram41415.11.2 Register Descriptions41615.11.3 Pin Configurations41815.12 Port A41915.12.1 Block Diagram41915.12.2 Register Descriptions42015.12.3 Pin Configurations42215.13 Port B42315.13.1 Block Diagram42315.13.2 Register Descriptions42415.13.3 Pin Configurations42615.14 Port C42715.14.1 Block Diagram42715.14.2 Register Descriptions42815.14.3 Pin Configurations42915.15 Treatment of Unused Pins430Chapter 16 Internal Flash Memory43116.1 Overview43216.2 Features43216.3 Block Diagram43216.4 Flash Memory Overwrite Mode and Settings43316.5 Flash Memory Mode43416.5.1 Description of External Pins43416.5.2 Erasure Blocks43716.6 On-board Write Mode438Chapter 17 Ordering Mask ROM43917.1 Overview44017.2 Procedure for Ordering ROM440Appendix443Appendix A. Register Map List444Appendix B. Instruction Set447Appendix C. Memory Connection Example453Appendix D. Pins and Their Operating Statuses upon Reset454Appendix E. Package Outline456Record of Changes457Colophon465Sales Offices466Dimensioni: 2,44 MBPagine: 466Language: EnglishApri il manuale
