Manuale UtenteSommarioINTRODUCTION5SYSTEM REQUIREMENTS5CONFIGURATIONS AND SETTINGS6POWER REQUIREMENTS6I2C MASTER SELECTION6USB INTERFACE7AUDIO INTERFACE7RESET7LOCATION OF MAJOR COMPONENTS7TEST PROGRAM 1301.EXE8INTRODUCTION8RUNNING THE TEST PROGRAM9USING MENUS9Choose I2C slave address for ISP13019Reset all registers9List all registers10Read/Write register10Select Mode of Operation11Enable/Disable charge-pump11HARDWARE DESCRIPTION12BLOCK DIAGRAM12FUNCTIONAL DESCRIPTION12PCF8584 I2C-bus controller12PC parallel to I2C converter12HC, DC and OTG core logic interface connector12Power manager13Audio interface13CONNECTOR PIN INFORMATION13DB-25 PC PARALLEL PORT CONNECTOR (J10) PIN ASSIGNMENT138-BIT MICROPROCESSOR INTERFACE 20 X 2 HEADER (J13) PIN ASSIGNMENT13USB OTG CONTROLLER INTERFACE 8 X 2 HEADER (J8 AND J3) PIN ASSIGNMENT13SCHEMATICS OF THE EVALUATION BOARD14BILL OF MATERIALS17REFERENCES18Table 3-1: +5.0 V power selection6Table 3-2: VBAT and VIO selection6Table 3-3: I C master selection6Table 7-1: DB-25 PC parallel port connector (J10) pin assignment13Table 7-2: 8-bit microprocessor-interface 20 x 2 header (J13) pin assignment[1]13Table 7-3: OTG Controller interface J8 pin assignment14Table 7-4: OTG Controller interface J3 pin assignment14Table 9-1: BOM of the ISP1301 evaluation board17Figure 1-1: ISP1301 evaluation board PCB layout5Figure 4-1: Location of major components8Figure 5-1: Test program main menu9Figure 5-2: List all registers screen display10Figure 5-3: Read/Write register screen display11Figure 5-4: Select Mode of Operation screen display11Figure 6-1: Block diagram of the ISP1301 evaluation board12Dimensioni: 299 KBPagine: 18Language: EnglishApri il manuale