Manuale UtenteSommario1. System Overview171.1. CIP-51™ Microcontroller Core211.1.1. Fully 8051 Compatible211.1.2. Improved Throughput211.1.3. Additional Features211.2. On-Chip Memory231.3. Universal Serial Bus Controller241.4. Voltage Regulator251.5. On-Chip Debug Circuitry251.6. Programmable Digital I/O and Crossbar261.7. Serial Ports271.8. Programmable Counter Array271.9. 10-Bit Analog to Digital Converter281.10.Comparators292. Absolute Maximum Ratings303. Global DC Electrical Characteristics314. Pinout and Package Definitions335. 10-Bit ADC (ADC0)415.1. Analog Multiplexer425.2. Temperature Sensor435.3. Modes of Operation455.3.1. Starting a Conversion455.3.2. Tracking Modes465.3.3. Settling Time Requirements475.4. Programmable Window Detector525.4.1. Window Detector In Single-Ended Mode545.4.2. Window Detector In Differential Mode556. Voltage Reference577. Comparators598. Voltage Regulator (REG0)698.1. Regulator Mode Selection698.2. VBUS Detection699. CIP-51 Microcontroller739.1. Instruction Set749.1.1. Instruction and CPU Timing749.1.2. MOVX Instruction and Program Memory759.2. Memory Organization799.2.1. Program Memory799.2.2. Data Memory809.2.3. General Purpose Registers809.2.4. Bit Addressable Locations809.2.5. Stack809.2.6. Special Function Registers819.2.7. Register Descriptions859.3. Interrupt Handler879.3.1. MCU Interrupt Sources and Vectors879.3.2. External Interrupts879.3.3. Interrupt Priorities889.3.4. Interrupt Latency889.3.5. Interrupt Register Descriptions899.4. Power Management Modes969.4.1. Idle Mode969.4.2. Stop Mode9610. Prefetch Engine9911. Reset Sources10111.1.Power-On Reset10211.2.Power-Fail Reset / VDD Monitor10311.3.External Reset10411.4.Missing Clock Detector Reset10411.5.Comparator0 Reset10411.6.PCA Watchdog Timer Reset10411.7.Flash Error Reset10411.8.Software Reset10511.9.USB Reset10512. Flash Memory10912.1.Programming The Flash Memory10912.1.1.Flash Lock and Key Functions10912.1.2.Flash Erase Procedure10912.1.3.Flash Write Procedure11012.2.Non-volatile Data Storage11112.3.Security Options11113. External Data Memory Interface and On-Chip XRAM11713.1.Accessing XRAM11713.1.1.16-Bit MOVX Example11713.1.2.8-Bit MOVX Example11713.2.Accessing USB FIFO Space11813.3.Configuring the External Memory Interface11913.4.Port Configuration11913.5.Multiplexed and Non-multiplexed Selection12213.5.1.Multiplexed Configuration12213.5.2.Non-multiplexed Configuration12313.6.Memory Mode Selection12313.6.1.Internal XRAM Only12413.6.2.Split Mode without Bank Select12413.6.3.Split Mode with Bank Select12513.6.4.External Only12513.7.Timing12513.7.1.Non-multiplexed Mode12713.7.2.Multiplexed Mode13014. Oscillators13514.1.Programmable Internal High-Frequency (H-F) Oscillator13614.1.1.Internal H-F Oscillator Suspend Mode13614.2.Programmable Internal Low-Frequency (L-F) Oscillator13714.2.1.Calibrating the Internal L-F Oscillator13714.3.External Oscillator Drive Circuit13914.3.1.Clocking Timers Directly Through the External Oscillator13914.3.2.External Crystal Example13914.3.3.External RC Example14014.3.4.External Capacitor Example14014.4.4x Clock Multiplier14214.5.System and USB Clock Selection14314.5.1.System Clock Selection14314.5.2.USB Clock Selection14315. Port Input/Output14715.1.Priority Crossbar Decoder14915.2.Port I/O Initialization15115.3.General Purpose Port I/O15416. Universal Serial Bus Controller (USB0)16316.1.Endpoint Addressing16416.2.USB Transceiver16416.3.USB Register Access16616.4.USB Clock Configuration17016.5.FIFO Management17116.5.1.FIFO Split Mode17116.5.2.FIFO Double Buffering17216.5.3.FIFO Access17216.6.Function Addressing17316.7.Function Configuration and Control17316.8.Interrupts17616.9.The Serial Interface Engine18016.10.Endpoint018016.10.1.Endpoint0 SETUP Transactions18116.10.2.Endpoint0 IN Transactions18116.10.3.Endpoint0 OUT Transactions18216.11.Configuring Endpoints1-318416.12.Controlling Endpoints1-3 IN18416.12.1.Endpoints1-3 IN Interrupt or Bulk Mode18416.12.2.Endpoints1-3 IN Isochronous Mode18516.13.Controlling Endpoints1-3 OUT18716.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode18716.13.2.Endpoints1-3 OUT Isochronous Mode18817. SMBus19317.1.Supporting Documents19417.2.SMBus Configuration19417.3.SMBus Operation19417.3.1.Arbitration19517.3.2.Clock Low Extension19617.3.3.SCL Low Timeout19617.3.4.SCL High (SMBus Free) Timeout19617.4.Using the SMBus19617.4.1.SMBus Configuration Register19817.4.2.SMB0CN Control Register20117.4.3.Data Register20417.5.SMBus Transfer Modes20417.5.1.Master Transmitter Mode20417.5.2.Master Receiver Mode20617.5.3.Slave Receiver Mode20717.5.4.Slave Transmitter Mode20817.6.SMBus Status Decoding20818. UART021118.1.Enhanced Baud Rate Generation21218.2.Operational Modes21218.2.1.8-Bit UART21318.2.2.9-Bit UART21418.3.Multiprocessor Communications21419. UART1 (C8051F340/1/4/5 Only)21919.1.Baud Rate Generator22019.2.Data Format22119.3.Configuration and Operation22219.3.1.Data Transmission22219.3.2.Data Reception22219.3.3.Multiprocessor Communications22320. Enhanced Serial Peripheral Interface (SPI0)22920.1.Signal Descriptions23020.1.1.Master Out, Slave In (MOSI)23020.1.2.Master In, Slave Out (MISO)23020.1.3.Serial Clock (SCK)23020.1.4.Slave Select (NSS)23020.2.SPI0 Master Mode Operation23120.3.SPI0 Slave Mode Operation23320.4.SPI0 Interrupt Sources23320.5.Serial Clock Timing23420.6.SPI Special Function Registers23621. Timers24321.1.Timer 0 and Timer 124321.1.1.Mode 0: 13-bit Counter/Timer24321.1.2.Mode 1: 16-bit Counter/Timer24421.1.3.Mode 2: 8-bit Counter/Timer with Auto-Reload24521.1.4.Mode 3: Two 8-bit Counter/Timers (Timer 0 Only)24621.2.Timer 225121.2.1.16-bit Timer with Auto-Reload25121.2.2.8-bit Timers with Auto-Reload25221.2.3.Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge25321.3.Timer 325721.3.1.16-bit Timer with Auto-Reload25721.3.2.8-bit Timers with Auto-Reload25821.3.3.USB Start-of-Frame Capture25922. Programmable Counter Array (PCA0)26322.1.PCA Counter/Timer26422.2.Capture/Compare Modules26522.2.1.Edge-triggered Capture Mode26622.2.2.Software Timer (Compare) Mode26722.2.3.High Speed Output Mode26822.2.4.Frequency Output Mode26922.2.5.8-Bit Pulse Width Modulator Mode27022.2.6.16-Bit Pulse Width Modulator Mode27122.3.Watchdog Timer Mode27222.3.1.Watchdog Timer Operation27222.3.2.Watchdog Timer Usage27322.4.Register Descriptions for PCA27423. C2 Interface27923.1.C2 Interface Registers27923.2.C2 Pin Sharing281Contact Information282Table 1.1. Product Selection Guide18Figure 1.1. C8051F340/1/4/5 Block Diagram19Figure 1.2. C8051F342/3/6/7 Block Diagram20Figure 1.3. On-Chip Clock and Reset22Figure 1.4. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6)23Figure 1.5. USB Controller Block Diagram24Figure 1.6. Digital Crossbar Diagram26Figure 1.7. PCA Block Diagram27Figure 1.8. PCA Block Diagram27Figure 1.9. 10-Bit ADC Block Diagram28Figure 1.10. Comparator0 Block Diagram29Table 2.1. Absolute Maximum Ratings30Table 3.1. Global DC Electrical Characteristics31Table 3.2. Index to Electrical Characteristics Tables32Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/733Figure 4.1. TQFP-48 Pinout Diagram (Top View)36Table 4.2. TQFP-48 Package Dimensions37Figure 4.2. TQFP-48 Package Diagram37Figure 4.3. LQFP-32 Pinout Diagram (Top View)38Table 4.3. LQFP-32 Package Dimensions39Figure 4.4. LQFP-32 Package Diagram39Figure 5.1. ADC0 Functional Block Diagram41Figure 5.2. Temperature Sensor Transfer Function43Figure 5.4. 10-Bit ADC Track and Conversion Example Timing46Figure 5.5. ADC0 Equivalent Input Circuits47Figure 5.7. ADC Window Compare Example: Left-Justified Single-Ended Data54Figure 5.8. ADC Window Compare Example: Right-Justified Differential Data55Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data55Table 5.1. ADC0 Electrical Characteristics56Figure 6.1. Voltage Reference Functional Block Diagram57Table 6.1. Voltage Reference Electrical Characteristics58Figure 7.1. Comparator Functional Block Diagram60Figure 7.2. Comparator Hysteresis Plot61Table 7.1. Comparator Electrical Characteristics68Table 8.1. Voltage Regulator Electrical Specifications69Figure 8.1. REG0 Configuration: USB Bus-Powered70Figure 8.2. REG0 Configuration: USB Self-Powered70Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled71Figure 8.4. REG0 Configuration: No USB Connection71Figure 9.1. CIP-51 Block Diagram73Table 9.1. CIP-51 Instruction Set Summary75Figure 9.2. Memory Map79Table 9.2. Special Function Register (SFR) Memory Map81Table 9.3. Special Function Registers82Table 9.4. Interrupt Summary89Figure 11.1. Reset Sources101Figure 11.2. Power-On and VDD Monitor Reset Timing102Table 11.1. Reset Electrical Characteristics107Table 12.1. Flash Electrical Characteristics111Figure 12.1. Flash Program Memory Map and Security Byte112Figure 13.2. Multiplexed Configuration Example122Figure 13.3. Non-multiplexed Configuration Example123Figure 13.4. EMIF Operating Modes123Figure 13.5. Non-multiplexed 16-bit MOVX Timing127Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing128Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing129Figure 13.8. Multiplexed 16-bit MOVX Timing130Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing131Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing132Table 13.1. AC Parameters for External Memory Interface133Figure 14.1. Oscillator Diagram135Table 14.1. Oscillator Electrical Characteristics145Figure 15.1. Port I/O Functional Block Diagram (Port 0 through Port 3)147Figure 15.2. Port I/O Cell Block Diagram148Figure 15.3. Crossbar Priority Decoder with No Pins Skipped149Figure 15.4. Crossbar Priority Decoder with Crystal Pins Skipped150Table 15.1. Port I/O DC Electrical Characteristics162Figure 16.1. USB0 Block Diagram163Table 16.1. Endpoint Addressing Scheme164Figure 16.2. USB0 Register Access Scheme166Table 16.2. USB0 Controller Registers169Figure 16.3. USB FIFO Allocation171Table 16.3. FIFO Configurations172Table 16.4. USB Transceiver Electrical Characteristics191Figure 17.1. SMBus Block Diagram193Figure 17.2. Typical SMBus Configuration194Figure 17.3. SMBus Transaction195Table 17.1. SMBus Clock Source Selection198Figure 17.4. Typical SMBus SCL Generation199Table 17.2. Minimum SDA Setup and Hold Times199Table 17.3. Sources for Hardware Changes to SMB0CN203Figure 17.5. Typical Master Transmitter Sequence205Figure 17.6. Typical Master Receiver Sequence206Figure 17.7. Typical Slave Receiver Sequence207Figure 17.8. Typical Slave Transmitter Sequence208Table 17.4. SMBus Status Decoding209Figure 18.1. UART0 Block Diagram211Figure 18.2. UART0 Baud Rate Logic212Figure 18.3. UART Interconnect Diagram213Figure 18.4. 8-Bit UART Timing Diagram213Figure 18.5. 9-Bit UART Timing Diagram214Figure 18.6. UART Multi-Processor Mode Interconnect Diagram215Using The Internal Oscillator218Figure 19.1. UART1 Block Diagram219Table 19.1. Baud Rate Generator Settings for Standard Baud Rates220Figure 19.2. UART1 Timing Without Parity or Extra Bit221Figure 19.3. UART1 Timing With Parity221Figure 19.4. UART1 Timing With Extra Bit221Figure 19.5. Typical UART Interconnect Diagram222Figure 19.6. UART Multi-Processor Mode Interconnect Diagram223Figure 20.1. SPI Block Diagram229Figure 20.2. Multiple-Master Mode Connection Diagram232Figure 20.3. 3-Wire Single Master and Slave Mode Connection Diagram232Figure 20.5. Master Mode Data/Clock Timing234Figure 20.6. Slave Mode Data/Clock Timing (CKPHA = 0)235Figure 20.7. Slave Mode Data/Clock Timing (CKPHA = 1)235Figure 20.8. SPI Master Timing (CKPHA = 0)239Figure 20.9. SPI Master Timing (CKPHA = 1)239Figure 20.10. SPI Slave Timing (CKPHA = 0)240Figure 20.11. SPI Slave Timing (CKPHA = 1)240Table 20.1. SPI Slave Timing Parameters241Figure 21.1. T0 Mode 0 Block Diagram244Figure 21.2. T0 Mode 2 Block Diagram245Figure 21.3. T0 Mode 3 Block Diagram246Figure 21.4. Timer 2 16-Bit Mode Block Diagram251Figure 21.5. Timer 2 8-Bit Mode Block Diagram252Figure 21.6. Timer 2 Capture Mode (T2SPLIT = ‘0’)253Figure 21.7. Timer 2 Capture Mode (T2SPLIT = ‘1’)254Figure 21.8. Timer 3 16-Bit Mode Block Diagram257Figure 21.9. Timer 3 8-Bit Mode Block Diagram258Figure 21.10. Timer 3 Capture Mode (T3SPLIT = ‘0’)259Figure 21.11. Timer 3 Capture Mode (T3SPLIT = ‘1’)260Figure 22.1. PCA Block Diagram263Table 22.1. PCA Timebase Input Options264Figure 22.2. PCA Counter/Timer Block Diagram264Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules265Figure 22.3. PCA Interrupt Block Diagram265Figure 22.4. PCA Capture Mode Diagram266Figure 22.5. PCA Software Timer Mode Diagram267Figure 22.6. PCA High Speed Output Mode Diagram268Figure 22.7. PCA Frequency Output Mode269Figure 22.8. PCA 8-Bit PWM Mode Diagram270Figure 22.9. PCA 16-Bit PWM Mode271Figure 22.10. PCA Module 4 with Watchdog Timer Enabled272Table 22.3. Watchdog Timer Timeout Intervals1273Figure 23.1. Typical C2 Pin Sharing281BitRate =3DutyCycle =256DutyCycle =65536Dimensioni: 2,13 MBPagine: 282Language: EnglishApri il manuale