Manuali utente per Silicon Laboratories SI5368

Sommario

• 1. Any-Frequency Precision Clock Product Family Overview

  12
• 2. Narrowband vs. Wideband Overview

  16
• 3. Any-Frequency Clock Family Members

  17
  • 3.1. Si5316

    17
  • 3.2. Si5319

    18
  • 3.3. Si5322

    19
  • 3.4. Si5323

    20
  • 3.5. Si5324

    21
  • 3.6. Si5325

    22
  • 3.7. Si5326

    23
  • 3.8. Si5327

    24
  • 3.9. Si5365

    25
  • 3.10. Si5366

    26
  • 3.11. Si5367

    27
  • 3.12. Si5368

    28
  • 3.13. Si5369

    29
  • 3.14. Si5374/75 Compared to Si5324/19

    29
  • 3.15. Si5374

    30
  • 3.16. Si5375

    31
• 4. Device Specifications

  32
• 5. DSPLL (All Devices)

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  • 5.1. Clock Multiplication

    47
  • 5.2. PLL Performance

    48
    • 5.2.1. Jitter Generation

      48
    • 5.2.2. Jitter Transfer

      48
    • 5.2.3. Jitter Tolerance

      49
• 6. Pin Control Parts (Si5316, Si5322, Si5323, Si5365, Si5366)

  50
  • 6.1. Clock Multiplication (Si5316, Si5322, Si5323, Si5365, Si5366)

    50
    • 6.1.1. Clock Multiplication (Si5316)

      50
    • 6.1.2. Clock Multiplication (Si5322, Si5323, Si5365, Si5366)

      52
    • 6.1.3. CKOUT3 and CKOUT4 (Si5365 and Si5366)

      64
    • 6.1.4. Loop bandwidth (Si5316, Si5322, Si5323, Si5365, Si5366)

      64
    • 6.1.5. Jitter Tolerance (Si5316, Si5323, Si5366)

      64
    • 6.1.6. Narrowband Performance (Si5316, Si5323, Si5366)

      64
    • 6.1.7. Input-to-Output Skew (Si5316, Si5323, Si5366)

      64
    • 6.1.8. Wideband Performance (Si5322 and Si5365)

      64
    • 6.1.9. Lock Detect (Si5322 and Si5365)

      64
    • 6.1.10. Input-to-Output Skew (Si5322 and Si5365)

      64
  • 6.2. PLL Self-Calibration

    65
    • 6.2.1. Input Clock Stability during Internal Self-Calibration (Si5316, Si5322, Si5323, Si5365, Si5366)

      65
    • 6.2.2. Self-Calibration caused by Changes in Input Frequency (Si5316, Si5322, Si5323, Si5365, Si5366)

      65
    • 6.2.3. Recommended Reset Guidelines (Si5316, Si5322, Si5323, Si5365, Si5366)

      65
  • 6.3. Pin Control Input Clock Control

    67
    • 6.3.1. Manual Clock Selection

      67
    • 6.3.2. Automatic Clock Selection (Si5322, Si5323, Si5365, Si5366)

      68
    • 6.3.3. Hitless Switching with Phase Build-Out (Si5323, Si5366)

      69
  • 6.4. Digital Hold/VCO Freeze

    70
    • 6.4.1. Narrowband Digital Hold (Si5316, Si5323, Si5366)

      70
    • 6.4.2. Recovery from Digital Hold (Si5316, Si5323, Si5366)

      70
    • 6.4.3. Wideband VCO Freeze (Si5322, Si5365)

      70
  • 6.5. Frame Synchronization (Si5366)

    70
  • 6.6. Output Phase Adjust (Si5323, Si5366)

    71
    • 6.6.1. FSYNC Realignment (Si5366)

      71
    • 6.6.2. Including FSYNC Inputs in Clock Selection (Si5366)

      71
    • 6.6.3. FS_OUT Polarity and Pulse Width Control (Si5366)

      71
    • 6.6.4. Using FS_OUT as a Fifth Output Clock (Si5366)

      71
    • 6.6.5. Disabling FS_OUT (Si5366)

      72
  • 6.7. Output Clock Drivers

    72
    • 6.7.1. LVPECL and CMOS TQFP Output Signal Format Restrictions at 3.3 V (Si5365, Si5366)

      72
  • 6.8. PLL Bypass Mode

    73
  • 6.9. Alarms

    73
    • 6.9.1. Loss-of-Signal Alarms (Si5316, Si5322, Si5323, Si5365, Si5366)

      73
    • 6.9.2. FOS Alarms (Si5365 and Si5366)

      73
    • 6.9.3. FSYNC Align Alarm (Si5366 and CK_CONF = 1 and FRQTBL = L)

      74
    • 6.9.4. C1B and C2B Alarm Outputs (Si5316, Si5322, Si5323)

      74
    • 6.9.5. C1B, C2B, C3B, and ALRMOUT Outputs (Si5365, Si5366)

      74
  • 6.10. Device Reset

    75
  • 6.11. DSPLLsim Configuration Software

    75
• 7. Microprocessor Controlled Parts (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

  76
  • 7.1. Clock Multiplication

    76
    • 7.1.1. Jitter Tolerance (Si5319, Si5324, Si5325, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375)

      76
    • 7.1.2. Wideband Parts (Si5325, Si5367)

      76
    • 7.1.3. Narrowband Parts (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

      77
    • 7.1.4. Loop Bandwidth (Si5319, Si5326, Si5368, Si5375)

      79
    • 7.1.5. Lock Detect (Si5319, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

      79
  • 7.2. PLL Self-Calibration

    79
    • 7.2.1. Initiating Internal Self-Calibration

      79
    • 7.2.2. Input Clock Stability during Internal Self-Calibration

      80
    • 7.2.3. Self-Calibration Caused by Changes in Input Frequency

      80
    • 7.2.4. Narrowband Input-to-Output Skew (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

      80
    • 7.2.5. Clock Output Behavior Before and During ICAL

      80
  • 7.3. Input Clock Configurations (Si5367 and Si5368)

    81
  • 7.4. Input Clock Control

    81
    • 7.4.1. Manual Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374)

      82
    • 7.4.2. Automatic Clock Selection (Si5324, Si5325, Si5326, Si5367, Si5368, Si5369, Si5374)

      83
    • 7.4.3. Hitless Switching with Phase Build-Out (Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)

      84
  • 7.5. Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374 and Si5375 Free Run Mode

    85
    • 7.5.1. Free Run Mode Programming Procedure

      85
    • 7.5.2. Clock Control Logic in Free Run Mode

      85
    • 7.5.3. Free Run Reference Frequency Constraints

      86
    • 7.5.4. Free Run Reference Frequency Constraints

      86
  • 7.6. Digital Hold

    87
    • 7.6.1. Narrowband Digital Hold (Si5316, Si5324, Si5326, Si5368, Si5369, Si5374)

      87
    • 7.6.2. History Settings for Low Bandwidth Devices (Si5324, Si5327, Si5369, Si5374)

      89
    • 7.6.3. Recovery from Digital Hold (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)

      89
    • 7.6.4. VCO Freeze (Si5319, Si5325, Si5367, Si5375)

      89
    • 7.6.5. Digital Hold versus VCO Freeze

      89
  • 7.7. Output Phase Adjust (Si5326, Si5368)

    90
    • 7.7.1. Coarse Skew Control (Si5326, Si5368)

      90
    • 7.7.2. Fine Skew Control (Si5326, Si5368)

      90
    • 7.7.3. Independent Skew (Si5324, Si5326, Si5368, Si5369, Si5374)

      91
    • 7.7.4. Output-to-output Skew (Si5324, Si5326, Si5327, Si5368, Si5369, Si5374)

      91
    • 7.7.5. Input-to-Output Skew (All Devices)

      91
  • 7.8. Frame Synchronization Realignment (Si5368 and CK_CONFIG_REG = 1)

    91
    • 7.8.1. FSYNC Realignment (Si5368)

      93
    • 7.8.2. FSYNC Skew Control (Si5368)

      94
    • 7.8.3. Including FSYNC Inputs in Clock Selection (Si5368)

      94
    • 7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)

      94
    • 7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368)

      94
  • 7.9. Output Clock Drivers (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

    95
    • 7.9.1. Disabling CKOUTn

      95
    • 7.9.2. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)

      95
  • 7.10. PLL Bypass Mode (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

    96
  • 7.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

    96
    • 7.11.1. Loss-of-Signal Alarms (Si5319, Si5324, Si5325, Si5326, Si5327, Si5367, Si5368, Si5369, Si5374, Si5375)

      96
    • 7.11.2. FOS Algorithm (Si5324, Si5325, Si5326, Si5368, Si5369, Si5374)

      97
    • 7.11.3. C1B, C2B (Si5319, Si5324, Si5325, Si5326, Si5327, Si5374, Si5375)

      99
    • 7.11.4. LOS (Si5319, Si5375)

      99
    • 7.11.5. C1B, C2B, C3B, ALRMOUT (Si5367, Si5368, Si5369 [CK_CONFIG_REG = 0])

      99
    • 7.11.6. C1B, C2B, C3B, ALRMOUT (Si5368 [CK_CONFIG_REG = 1])

      100
    • 7.11.7. LOS Algorithm for Reference Clock Input (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

      100
    • 7.11.8. LOL (Si5319, Si5324, Si5326, Si5327, Si5368, Si5369, Si5374, Si5375)

      100
    • 7.11.9. Device Interrupts

      101
  • 7.12. Device Reset

    101
  • 7.13. I2C Serial Microprocessor Interface

    102
  • 7.14. Serial Microprocessor Interface (SPI)

    103
    • 7.14.1. Default Device Configuration

      104
  • 7.15. Register Descriptions

    104
  • 7.16. DSPLLsim Configuration Software

    104
• 8. High-Speed I/O

  105
  • 8.1. Input Clock Buffers

    105
  • 8.2. Output Clock Drivers

    107
    • 8.2.1. LVPECL TQFP Output Signal Format Restrictions at 3.3 V (Si5367, Si5368, Si5369)

      107
    • 8.2.2. Typical Output Circuits

      107
    • 8.2.3. Typical Clock Output Scope Shots

      109
  • 8.3. Typical Scope Shots for SFOUT Options

    110
  • 8.4. Crystal/Reference Clock Interfaces (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, and Si5375)

    113
  • 8.5. Three-Level (3L) Input Pins (No External Resistors)

    115
  • 8.6. Three-Level (3L) Input Pins (With External Resistors)

    116
• 9. Power Supply

  117
• 10. Packages and Ordering Guide

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• Appendix A—Narrowband References

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• Appendix B—Frequency Plans and Jitter Performance (Si5316, Si5319, Si5323, Si5324, Si5326, Si5327, Si5366, Si5368, Si5369, Si5374, Si5375)

  121
• Appendix C—Typical Phase Noise Plots

  126
• Appendix D—Alarm Structure

  144
• Appendix E—Internal Pullup, Pulldown by Pin

  147
• Appendix F—Typical Performance: Bypass Mode, PSRR, Crosstalk, Output Format Jitter

  154
• Appendix G—Near Integer Ratios

  162
• Appendix H—Jitter Attenuation and Loop BW

  164
• Appendix I—Si5374 and Si5375 PCB Layout Recommendations

  169
• Appendix J—Si5374 and Si5375 Crosstalk

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• Document Change List

  178
• Contact Information

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