Manuali utente per Texas Instruments SM320F2812-HT

Sommario

• Table of Contents

  2
• 1  Features

  11
  • 1.1 SUPPORTS EXTREME TEMPERATURE APPLICATIONS

    12
• 2 Introduction

  13
  • 2.1 Description

    13
  • 2.2 Device Summary

    14
  • 2.3 Die Layout

    15
  • 2.4 Pin Assignments

    16
  • 2.5 Signal Descriptions

    17
• 3 Functional Overview

  27
  • 3.1 Memory Map

    28
  • 3.2 Brief Descriptions

    31
    • 3.2.1 C28x CPU

      31
    • 3.2.2 Memory Bus (Harvard Bus Architecture)

      31
    • 3.2.3 Peripheral Bus

      31
    • 3.2.4 Real-Time JTAG and Analysis

      31
    • 3.2.5 External Interface (XINTF)

      32
    • 3.2.6 Flash

      32
    • 3.2.7 L0, L1, H0 SARAMs

      32
    • 3.2.8 Boot ROM

      32
    • 3.2.9 Security

      33
    • 3.2.10 Peripheral Interrupt Expansion (PIE) Block

      34
    • 3.2.11 External Interrupts (XINT1, XINT2, XINT13, XNMI)

      34
    • 3.2.12 Oscillator and PLL

      34
    • 3.2.13 Watchdog

      34
    • 3.2.14 Peripheral Clocking

      34
    • 3.2.15 Low-Power Modes

      34
    • 3.2.16 Peripheral Frames 0, 1, 2 (PFn)

      35
    • 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer

      35
    • 3.2.18 32-Bit CPU Timers (0, 1, 2)

      35
    • 3.2.19 Control Peripherals

      35
    • 3.2.20 Serial Port Peripherals

      36
  • 3.3 Register Map

    36
  • 3.4 Device Emulation Registers

    39
  • 3.5 External Interface, XINTF

    39
    • 3.5.1 Timing Registers

      41
    • 3.5.2 XREVISION Register

      41
  • 3.6 Interrupts

    42
    • 3.6.1 External Interrupts

      45
  • 3.7 System Control

    46
  • 3.8 OSC and PLL Block

    48
    • 3.8.1 Loss of Input Clock

      49
  • 3.9 PLL-Based Clock Module

    49
  • 3.10 External Reference Oscillator Clock Option

    49
  • 3.11 Watchdog Block

    50
  • 3.12 Low-Power Modes Block

    51
• 4 Peripherals

  52
  • 4.1 32-Bit CPU-Timers 0/1/2

    52
  • 4.2 Event Manager Modules (EVA, EVB)

    55
    • 4.2.1 General-Purpose (GP) Timers

      58
    • 4.2.2 Full-Compare Units

      58
    • 4.2.3 Programmable Deadband Generator

      58
    • 4.2.4 PWM Waveform Generation

      58
    • 4.2.5 Double Update PWM Mode

      58
    • 4.2.6 PWM Characteristics

      59
    • 4.2.7 Capture Unit

      59
    • 4.2.8 Quadrature-Encoder Pulse (QEP) Circuit

      59
    • 4.2.9 External ADC Start-of-Conversion

      59
  • 4.3 Enhanced Analog-to-Digital Converter (ADC) Module

    60
  • 4.4 Enhanced Controller Area Network (eCAN) Module

    65
  • 4.5 Multichannel Buffered Serial Port (McBSP) Module

    69
  • 4.6 Serial Communications Interface (SCI) Module

    73
  • 4.7 Serial Peripheral Interface (SPI) Module

    76
  • 4.8 GPIO MUX

    79
• 5 Development Support

  82
  • 5.1 Device and Development Support Tool Nomenclature

    82
  • 5.2 Documentation Support

    83
• 6 Electrical Specifications

  85
  • 6.1 Absolute Maximum Ratings

    85
  • 6.2  Recommended Operating Conditions

    86
  • 6.3  Electrical Characteristics

    86
  • 6.4 Current Consumption by Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes at 150-MHz SYSCLKOUT

    88
  • 6.5 Current Consumption Graphs

    89
  • 6.6 Reducing Current Consumption

    90
  • 6.7 Power Sequencing Requirements

    90
  • 6.8 Signal Transition Levels

    91
  • 6.9 Timing Parameter Symbology

    92
  • 6.10 General Notes on Timing Parameters

    93
  • 6.11 Test Load Circuit

    93
  • 6.12 Device Clock Table

    94
  • 6.13 Clock Requirements and Characteristics

    94
    • 6.13.1 Input Clock Requirements

      94
    • 6.13.2 Output Clock Characteristics

      95
  • 6.14 Reset Timing

    96
  • 6.15 Low-Power Mode Wakeup Timing

    100
  • 6.16 Event Manager Interface

    104
    • 6.16.1 PWM Timing

      104
    • 6.16.2 Interrupt Timing

      106
  • 6.17 General-Purpose Input/Output (GPIO) – Output Timing

    107
  • 6.18 General-Purpose Input/Output (GPIO) – Input Timing

    108
  • 6.19 SPI Master Mode Timing

    109
  • 6.20 SPI Slave Mode Timing

    113
  • 6.21 External Interface (XINTF) Timing

    117
  • 6.22 XINTF Signal Alignment to XCLKOUT

    121
  • 6.23 External Interface Read Timing

    122
  • 6.24 External Interface Write Timing

    123
  • 6.25 External Interface Ready-on-Read Timing With One External Wait State

    125
  • 6.26 External Interface Ready-on-Write Timing With One External Wait State

    128
  • 6.27  XHOLD and XHOLDA

    131
  • 6.28  XHOLD/XHOLDA Timing

    132
  • 6.29 On-Chip Analog-to-Digital Converter

    134
    • 6.29.1 ADC Absolute Maximum Ratings

      134
    • 6.29.2 ADC Electrical Characteristics Over Recommended Operating Conditions

      135
    • 6.29.3 Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK)

      136
    • 6.29.4 ADC Power-Up Control Bit Timing

      137
    • 6.29.5 Detailed Description

      138
      • 6.29.5.1 Reference Voltage

        138
      • 6.29.5.2 Analog Inputs

        138
      • 6.29.5.3 Converter

        138
      • 6.29.5.4 Conversion Modes

        138
    • 6.29.6 Sequential Sampling Mode (Single Channel) (SMODE = 0)

      138
    • 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)

      140
    • 6.29.8 Definitions of Specifications and Terminology

      141
      • 6.29.8.1 Integral Nonlinearity

        141
      • 6.29.8.2 Differential Nonlinearity

        141
      • 6.29.8.3 Zero Offset

        141
      • 6.29.8.4 Gain Error

        141
      • 6.29.8.5 Signal-to-Noise Ratio + Distortion (SINAD)

        141
      • 6.29.8.6 Effective Number of Bits (ENOB)

        141
      • 6.29.8.7 Total Harmonic Distortion (THD)

        141
      • 6.29.8.8 Spurious Free Dynamic Range (SFDR)

        141
  • 6.30 Multichannel Buffered Serial Port (McBSP) Timing

    142
    • 6.30.1 McBSP Transmit and Receive Timing

      142
    • 6.30.2 McBSP as SPI Master or Slave Timing

      145
  • 6.31 Flash Timing

    149
    • 6.31.1 Recommended Operating Conditions

      149
• 7 Mechanical Data

  151