Manuali utente per Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE

Sommario

• 1 Features

  1
  • 1.1 CTZ/ZTZ BGA Package (Bottom View)

    2
  • 1.2 Description

    3
  • 1.3  Functional Block Diagram

    4
• Table of Contents

  5
• Revision History

  6
• 2 Device Overview

  7
  • 2.1 Device Characteristics

    7
  • 2.2 CPU (DSP Core) Description

    8
  • 2.3 Memory Map Summary

    11
  • 2.4 Boot Mode Sequence

    14
    • 2.4.1 Boot Modes Supported

      14
    • 2.4.2 BOOTACTIVE

      18
  • 2.5 Pin Assignments

    19
    • 2.5.1 Pin Map

      19
  • 2.6 Signal Groups Description

    23
  • 2.7 Terminal Functions

    29
  • 2.8 Development

    53
    • 2.8.1 Development Support

      53
    • 2.8.2 Device Support

      53
      • 2.8.2.1 Device and Development-Support Tool Nomenclature

        53
      • 2.8.2.2  Documentation Support

        54
  • 2.9 Community Resources

    58
• 3 Device Configuration

  59
  • 3.1 Device Configuration at Device Reset

    59
    • 3.1.1 Debugging Considerations

      60
  • 3.2 Device Configuration Register Descriptions

    60
  • 3.3 Peripheral Selection After Device Reset

    63
    • 3.3.1 Controlling Internal Pulls on the Peripherals

      63
      • 3.3.1.1 Device Control Register (DEVCTL)

        63
      • 3.3.1.2 Device Control Key Register (DEVCTL_KEY)

        65
      • 3.3.1.3 IPU/IPD Control

        66
  • 3.4 Device Status Register (DEVSTAT)

    73
  • 3.5 RMIIn Reset Registers (RMIIRESET0 and RMIIRESET1)

    74
  • 3.6 Memory Privilege Registers

    75
    • 3.6.1 Host Memory Privilege Permission Register (HOSTPRIV)

      75
    • 3.6.2 Memory Privilege Permission Register (PRIVPERM)

      76
    • 3.6.3 Key-Based Protection for HOSTPRIV and PRIVPERM Registers (PRIVKEY)

      77
  • 3.7 Host and Inter-DSP Interrupt Registers

    78
    • 3.7.1 NMI Generator Registers (NMIGR0-NMIGR5)

      78
    • 3.7.2 Inter-DSP Interrupt Registers (IPCGR0-IPCGR5 and IPCAR0-IPCAR5)

      79
    • 3.7.3 Host Interrupt and Event Pulse Generation Registers (IPCGR15 and IPCAR15)

      81
  • 3.8 Timer Event Manager Registers

    83
    • 3.8.1 Timer Pin Manager Register (TPMGR)

      83
    • 3.8.2 Reset Mux Registers (RSTMUX0-RSTMUX5)

      84
  • 3.9 Reset and Boot Registers

    85
    • 3.9.1 Reset Status Register (RESET_STAT)

      85
    • 3.9.2 Boot Complete Status Register (BOOT_COMPLETE_STAT)

      86
    • 3.9.3 Boot Progress Register (BOOTPROGRESS)

      87
    • 3.9.4 BOOTMODEn Register (BOOTMODE0-BOOTMODE5)

      87
    • 3.9.5 DSP_BOOT_ADDRn Register (DSP_BOOT_ADDR0-DSP_BOOT_ADDR5)

      88
  • 3.10 JTAG ID Register Description

    89
  • 3.11 Silicon Revision ID Register Description

    89
• 4 System Interconnect

  90
  • 4.1 Internal Buses, Bridges, and Switch Fabrics

    90
  • 4.2 Data Switch Fabric Connections

    91
  • 4.3 Priority Allocation

    94
  • 4.4 Configuration Switch Fabric

    94
• 5 C64x+ Megamodule

  96
  • 5.1 Memory Architecture

    96
  • 5.2 Memory Protection Support

    100
  • 5.3 Bandwidth Management

    101
  • 5.4 Power-Down Control

    102
  • 5.5 Megamodule Resets

    102
  • 5.6 Megamodule Revision

    103
  • 5.7 C64x+ Megamodule Register Descriptions

    104
  • 5.8 CPU Revision ID

    112
• 6 Device Operating Conditions

  113
  • 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

    113
  • 6.2 Recommended Operating Conditions

    114
  • 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

    116
• 7 C64x+ Peripheral Information and Electrical Specifications

  118
  • 7.1 Parameter Information

    118
    • 7.1.1  3.3-V Signal Transition Levels

      118
    • 7.1.2  3.3-V Signal Transition Rates

      118
    • 7.1.3  Timing Parameters and Board Routing Analysis

      118
  • 7.2 Recommended Clock and Control Signal Transition Behavior

    119
  • 7.3 Power Supplies

    119
    • 7.3.1 Power-Supply Sequencing

      119
    • 7.3.2 Power-Supply Decoupling

      120
    • 7.3.3 Preserving Boundary-Scan Functionality on DDR2, RGMII, and RapidIO Interface Pins

      120
  • 7.4 Power and Sleep Controller (PSC)

    121
    • 7.4.1 PSC Peripheral Register Descriptions

      123
  • 7.5 Enhanced Direct Memory Access (EDMA3) Controller

    124
    • 7.5.1 EDMA3 Channel Synchronization Events

      124
    • 7.5.2 EDMA3 Peripheral Register Descriptions

      126
  • 7.6 Interrupts

    137
    • 7.6.1 Interrupt Sources and Interrupt Controller

      137
    • 7.6.2 NMI Pin-Generated Interrupts

      140
    • 7.6.3 GPIO Pin-Generated Interrupts

      140
    • 7.6.4 Host and Inter-DSP Interrupts

      140
  • 7.7 Reset Controller

    141
    • 7.7.1 Power-on Reset

      141
    • 7.7.2 Warm Reset (RESET Pin)

      142
    • 7.7.3 System Reset

      143
    • 7.7.4 Local Reset

      143
    • 7.7.5 Module Reset

      144
    • 7.7.6 Reset Priority

      144
    • 7.7.7 Reset Controller Register

      144
      • 7.7.7.1 Reset Type Status Register Description

        144
    • 7.7.8 Reset Electrical Data/Timing

      145
  • 7.8 PLL1 and PLL1 Controller

    149
    • 7.8.1 PLL1 Controller Device-Specific Information

      149
      • 7.8.1.1 Internal Clocks and Maximum Operating Frequencies

        149
      • 7.8.1.2 PLL1 Controller Operating Modes

        151
      • 7.8.1.3 PLL1 Stabilization, Lock, and Reset Times

        151
    • 7.8.2 PLL1 Controller Peripheral Register Descriptions

      152
    • 7.8.3 PLL1 Controller Registers

      153
      • 7.8.3.1 PLL1 Peripheral ID Register (PID)

        153
      • 7.8.3.2 Reset Type Status Register (RSTYPE)

        153
      • 7.8.3.3 PLL1 PLL Control Register (PLLCTL)

        154
      • 7.8.3.4 PLL1 PLL Multiply Control Register (PLLM)

        155
      • 7.8.3.5 PLL1 PLL Controller Divider Register (PLLDIV10)

        155
      • 7.8.3.6 PLL1 PLL Controller Command Register (PLLCMD)

        156
      • 7.8.3.7 PLL1 PLL Controller Status Register (PLLSTAT)

        157
      • 7.8.3.8 PLL1 PLLDIV Ratio Change Status Register (DCHANGE)

        158
      • 7.8.3.9 PLL1 SYSCLK Status Register (SYSTAT)

        159
    • 7.8.4 PLL1 Controller Input and Output Clock Electrical Data/Timing

      160
  • 7.9 PLL2 and PLL2 Controller

    161
    • 7.9.1 PLL2 Controller Device-Specific Information

      161
      • 7.9.1.1 Internal Clocks and Maximum Operating Frequencies

        161
      • 7.9.1.2 PLL2 Controller

        162
      • 7.9.1.3 PLL2 Stabilization, Lock, and Reset Times

        162
    • 7.9.2 PLL2 Controller Peripheral Register Descriptions

      163
    • 7.9.3 PLL2 Controller Registers

      164
      • 7.9.3.1 PLL2 Peripheral ID Register (PID)

        164
      • 7.9.3.2 PLL2 PLL Control Register (PLLCTL)

        165
      • 7.9.3.3 PLL2 PLL Controller Dividern Register (PLLDIVn)

        166
      • 7.9.3.4 PLL2 PLL Controller Command Register (PLLCMD)

        167
      • 7.9.3.5 PLL2 PLL Controller Status Register (PLLSTAT)

        168
      • 7.9.3.6 PLL2 PLLDIV Ratio Change Status Register (DCHANGE)

        169
      • 7.9.3.7 PLL2 SYSCLK Status Register (SYSTAT)

        170
    • 7.9.4 PLL2 Controller Input Clock Electrical Data/Timing

      171
  • 7.10 PLL3 and PLL3 Controller

    172
    • 7.10.1 PLL3 Controller Device-Specific Information

      172
      • 7.10.1.1 Internal Clocks and Maximum Operating Frequencies

        172
      • 7.10.1.2 PLL3 Controller

        172
      • 7.10.1.3 PLL3 Stabilization, Lock, and Reset Times

        172
    • 7.10.2 PLL3 Controller Peripheral Register Descriptions

      173
    • 7.10.3 PLL3 Controller Registers

      173
      • 7.10.3.1 PLL3 Peripheral ID Register

        174
      • 7.10.3.2 PLL3 PLL Control Register (PLLCTL)

        174
    • 7.10.4 PLL3 Controller Input and Output Clock Electrical Data/Timing

      175
  • 7.11 DDR2 Memory Controller

    176
    • 7.11.1 DDR2 Memory Controller Device-Specific Information

      176
    • 7.11.2 DDR2 Memory Controller Peripheral Register Descriptions

      176
    • 7.11.3 DDR2 Memory Controller Electrical Data/Timing

      177
  • 7.12 I2C Peripheral

    178
    • 7.12.1 I2C Device-Specific Information

      178
    • 7.12.2 I2C Peripheral Register Descriptions

      180
    • 7.12.3 I2C Electrical Data/Timing

      181
  • 7.13 Host-Port Interface (HPI) Peripheral

    183
    • 7.13.1 HPI Device-Specific Information

      183
    • 7.13.2 HPI Peripheral Register Descriptions

      183
    • 7.13.3 Host Access to HPI

      183
    • 7.13.4 HPI Electrical Data/Timing

      184
  • 7.14 TSIP

    190
    • 7.14.1 TSIP0 Peripheral Register Descriptions

      190
    • 7.14.2 TSIP1 Peripheral Register Descriptions

      198
    • 7.14.3 TSIP2 Peripheral Register Descriptions

      206
    • 7.14.4 TSIP Electrical Data/Timing

      214
  • 7.15 Ethernet MAC (EMAC)

    216
    • 7.15.1 EMAC Device-Specific Information

      217
    • 7.15.2 EMAC Peripheral Register Descriptions

      219
    • 7.15.3 EMIC Peripheral Register Descriptions

      226
    • 7.15.4 EMAC Electrical Data/Timing (MII, GMII, RMII, RGMII, and SSMII)

      227
      • 7.15.4.1 EMAC MII and GMII Electrical Data/Timing

        227
      • 7.15.4.2  EMAC RMII Electrical Data/Timing

        230
      • 7.15.4.3  EMAC RGMII Electrical Data/Timing

        231
      • 7.15.4.4 EMAC SSMII Electrical Data/Timing

        234
    • 7.15.5  Management Data Input/Output (MDIO)

      235
      • 7.15.5.1 MDIO Device-Specific Information

        235
      • 7.15.5.2 MDIO Peripheral Register Descriptions

        235
      • 7.15.5.3 MDIO Electrical Data/Timing

        236
  • 7.16 Timers

    237
    • 7.16.1 Timer Device-Specific Information

      237
    • 7.16.2 Timer Peripheral Register Descriptions

      237
    • 7.16.3 Timer Electrical Data/Timing

      242
  • 7.17 UTOPIA

    243
    • 7.17.1 UTOPIA Device-Specific Information

      243
    • 7.17.2 UTOPIA Peripheral Register Descriptions

      243
    • 7.17.3 UTOPIA Electrical Data/Timing

      245
  • 7.18 Serial RapidIO (SRIO) Port

    248
    • 7.18.1 Serial RapidIO Device-Specific Information

      248
    • 7.18.2 SRIO Peripheral Register Descriptions

      248
  • 7.19 General-Purpose Input/Output (GPIO)

    259
    • 7.19.1 GPIO Device-Specific Information

      259
    • 7.19.2 GPIO Peripheral Register Descriptions

      259
    • 7.19.3 GPIO Electrical Data/Timing

      259
  • 7.20 Emulation Features and Capability

    261
    • 7.20.1 Advanced Event Triggering (AET)

      261
    • 7.20.2 Trace

      261
    • 7.20.3 IEEE 1149.1 JTAG

      262
      • 7.20.3.1 IEEE 1149.1 JTAG Compatibility Statement

        262
      • 7.20.3.2 Boundary Scan Operation

        262
      • 7.20.3.3 JTAG Electrical Data/Timing

        263
• 8 Mechanical Data

  264
  • 8.1 Thermal Data

    264
  • 8.2 Packaging Information

    264