Manuali utente per Texas Instruments TMS320C64x DSP

Sommario

• IMPORTANT NOTICE

  2
• Read This First

  3
  • About This Manual

    3
  • Notational Conventions

    3
  • Related Documentation From Texas Instruments

    3
  • Trademarks

    4
• Contents

  5
• Figures

  11
• Tables

  15
• Chapter 1: Overview

  18
  • 1.1 Video Port

    19
  • 1.2 Video Port FIFO

    22
    • 1.2.1 DMA Interface

      22
    • 1.2.2 Video Capture FIFO Configurations

      23
    • 1.2.3 Video Display FIFO Configurations

      26
  • 1.3 Video Port Registers

    29
  • 1.4 Video Port Pin Mapping

    30
    • 1.4.1 VDIN Bus Usage for Capture Modes

      32
    • 1.4.2 VDOUT Data Bus Usage for Display Modes

      33
• Chapter 2: Video Port

  34
  • 2.1 Reset Operation

    35
    • 2.1.1 Power-On Reset

      35
    • 2.1.2 Peripheral Bus Reset

      35
    • 2.1.3 Software Port Reset

      36
    • 2.1.4 Capture Channel Reset

      36
    • 2.1.5 Display Channel Reset

      37
  • 2.2 Interrupt Operation

    38
  • 2.3 DMA Operation

    39
    • 2.3.1 Capture DMA Event Generation

      39
    • 2.3.2 Display DMA Event Generation

      41
    • 2.3.3 DMA Size and Threshold Restrictions

      43
    • 2.3.4 DMA Interface Operation

      44
  • 2.4 Clocks

    45
  • 2.5 Video Port Functionality Subsets

    45
    • 2.5.1 Data Bus Width

      45
    • 2.5.2 FIFO Size

      46
  • 2.6 Video Port Throughput and Latency

    46
    • 2.6.1 Video Capture Throughput

      46
    • 2.6.2 Video Display Throughput

      48
  • 2.7 Video Port Control Registers

    49
    • 2.7.1 Video Port Control Register (VPCTL)

      50
    • 2.7.2 Video Port Status Register (VPSTAT)

      53
    • 2.7.3 Video Port Interrupt Enable Register (VPIE)

      54
    • 2.7.4 Video Port Interrupt Status Register (VPIS)

      57
• Chapter 3: Video Capture Port

  63
  • 3.1 Video Capture Mode Selection

    64
  • 3.2 BT.656 Video Capture Mode

    65
    • 3.2.1 BT.656 Capture Channels

      65
    • 3.2.2 BT.656 Timing Reference Codes

      66
    • 3.2.3 BT.656 Image Window and Capture

      68
    • 3.2.4 BT.656 Data Sampling

      70
    • 3.2.5 BT.656 FIFO Packing

      71
  • 3.3 Y/C Video Capture Mode

    74
    • 3.3.1 Y/C Capture Channels

      74
    • 3.3.2 Y/C Timing Reference Codes

      74
    • 3.3.3 Y/C Image Window and Capture

      75
    • 3.3.4 Y/C FIFO Packing

      76
  • 3.4 BT.656 and Y/C Mode Field and Frame Operation

    79
    • 3.4.1 Capture Determination and Notification

      79
    • 3.4.2 Vertical Synchronization

      81
    • 3.4.3 Horizontal Synchronization

      84
    • 3.4.4 Field Identification

      86
    • 3.4.5 Short and Long Field Detect

      87
  • 3.5 Video Input Filtering

    88
    • 3.5.1 Input Filter Modes

      88
    • 3.5.2 Chrominance Resampling Operation

      89
    • 3.5.3 Scaling Operation

      89
    • 3.5.4 Edge Pixel Replication

      91
  • 3.6 Ancillary Data Capture

    93
    • 3.6.1 Horizontal Ancillary (HANC) Data Capture

      93
    • 3.6.2 Vertical Ancillary (VANC) Data Capture

      93
  • 3.7 Raw Data Capture Mode

    94
    • 3.7.1 Raw Data Capture Notification

      94
    • 3.7.2 Raw Data FIFO Packing

      95
  • 3.8 TSI Capture Mode

    99
    • 3.8.1 TSI Capture Features

      99
    • 3.8.2 TSI Data Capture

      99
    • 3.8.3 TSI Capture Error Detection

      100
    • 3.8.4 Synchronizing the System Clock

      100
    • 3.8.5 TSI Data Capture Notification

      102
    • 3.8.6 Writing to the FIFO

      103
    • 3.8.7 Reading from the FIFO

      104
  • 3.9 Capture Line Boundary Conditions

    104
  • 3.10 Capturing Video in BT.656 or Y/C Mode

    106
    • 3.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode

      107
  • 3.11 Capturing Video in Raw Data Mode

    108
    • 3.11.1 Handling FIFO Overrun Condition in Raw Data Mode

      109
  • 3.12 Capturing Data in TSI Capture Mode

    109
    • 3.12.1 Handling FIFO Overrun Condition in TSI Capture Mode

      110
  • 3.13 Video Capture Registers

    111
    • 3.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT)

      112
    • 3.13.2 Video Capture Channel A Control Register (VCACTL)

      115
    • 3.13.3 Video Capture Channel x Field 1 Start Register (VCASTRT1, VCBSTR\ T1)

      120
    • 3.13.4 Video Capture Channel x Field 1 Stop Register (VCASTOP1, VCBSTOP\ 1)

      122
    • 3.13.5 Video Capture Channel x Field 2 Start Register (VCASTRT2, VCBSTR\ T2)

      123
    • 3.13.6 Video Capture Channel x Field 2 Stop Register (VCASTOP2, VCBSTOP\ 2)

      124
    • 3.13.7 Video Capture Channel x Vertical Interrupt Register (VCAVINT, VC\ BVINT)

      125
    • 3.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD)\

      127
    • 3.13.9 Video Capture Channel x Event Count Register (VCAEVTCT, VCBEVTCT\ )

      129
    • 3.13.10 Video Capture Channel B Control Register (VCBCTL)

      130
    • 3.13.11 TSI Capture Control Register (TSICTL)

      134
    • 3.13.12 TSI Clock Initialization LSB Register (TSICLKINITL)

      136
    • 3.13.13 TSI Clock Initialization MSB Register (TSICLKINITM)

      137
    • 3.13.14 TSI System Time Clock LSB Register (TSISTCLKL)

      138
    • 3.13.15 TSI System Time Clock MSB Register (TSISTCLKM)

      139
    • 3.13.16 TSI System Time Clock Compare LSB Register (TSISTCMPL)

      140
    • 3.13.17 TSI System Time Clock Compare MSB Register (TSISTCMPM)

      141
    • 3.13.18 TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)

      142
    • 3.13.19 TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)

      143
    • 3.13.20 TSI System Time Clock Ticks Interrupt Register (TSITICKS)

      144
  • 3.14 Video Capture FIFO Registers

    145
• Chapter 4: Video Display Port

  146
  • 4.1 Video Display Mode Selection

    147
    • 4.1.1 Image Timing

      147
    • 4.1.2 Video Display Counters

      150
    • 4.1.3 Sync Signal Generation

      152
    • 4.1.4 External Sync Operation

      153
    • 4.1.5 Port Sync Operation

      153
  • 4.2 BT.656 Video Display Mode

    154
    • 4.2.1 Display Timing Reference Codes

      154
    • 4.2.2 Blanking Codes

      157
    • 4.2.3 BT.656 Image Display

      157
    • 4.2.4 BT.656 FIFO Unpacking

      158
  • 4.3 Y/C Video Display Mode

    161
    • 4.3.1 Y/C Display Timin Reference Codes

      161
    • 4.3.2 Y/C Blanking Codes

      162
    • 4.3.3 Y/C Image Display

      162
    • 4.3.4 Y/C FIFO Unpacking

      162
  • 4.4 Video Output Filtering

    166
    • 4.4.1 Output Filter Modes

      166
    • 4.4.2 Chrominance Resampling Operation

      167
    • 4.4.3 Scaling Operation

      167
    • 4.4.4 Edge Pixel Replication

      168
  • 4.5 Ancillary Data Display

    170
    • 4.5.1 Horizontal Ancillary (HANC) Data Display

      170
    • 4.5.2 Vertical Ancillary (VANC) Data Display

      170
  • 4.6 Raw Data Display Mode

    170
    • 4.6.1 Raw Mode RGB Output Support

      171
    • 4.6.2 Raw Data FIFO Unpacking

      171
  • 4.7 Video Display Field and Frame Operation

    175
    • 4.7.1 Display Determination and Notification

      175
    • 4.7.2 Video Display Event Generation

      177
  • 4.8 Display Line Boundary Conditions

    178
  • 4.9 Display Timing Examples

    180
    • 4.9.1 Interlaced BT.656 Timing Example

      180
    • 4.9.2 Interlaced Raw Display Example

      184
    • 4.9.3 Y/C Progressive Display Example

      188
  • 4.10 Displaying Video in BT.656 or Y/C Mode

    192
  • 4.11 Displaying Video in Raw Data Mode

    194
    • 4.11.1 Handling Underrun Condition of the Display FIFO

      196
  • 4.12 Video Display Registers

    197
    • 4.12.1 Video Display Status Register (VDSTAT)

      198
    • 4.12.2 Video Display Control Register (VDCTL)

      200
    • 4.12.3 Video Display Frame Size Register (VDFRMSZ)

      205
    • 4.12.4 Video Display Horizontal Blanking Register (VDHBLNK)

      206
    • 4.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1\ )

      207
    • 4.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)\

      209
    • 4.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2\ )

      210
    • 4.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)\

      212
    • 4.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1)

      213
    • 4.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1)

      215
    • 4.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2)

      216
    • 4.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2)

      218
    • 4.12.13 Video Display Field 1 Timing Register (VDFLDT1)

      219
    • 4.12.14 Video Display Field 2 Timing Register (VDFLDT2)

      220
    • 4.12.15 Video Display Threshold Register (VDTHRLD)

      221
    • 4.12.16 Video Display Horizontal Synchronization Register (VDHSYNC)

      223
    • 4.12.17 Video Display Field 1 Vertical Synchronization Start Register (\ VDVSYNS1)

      224
    • 4.12.18 Video Display Field 1 Vertical Synchronization End Register (VD\ VSYNE1)

      225
    • 4.12.19 Video Display Field 2 Vertical Synchronization Start Register (\ VDVSYNS2)

      226
    • 4.12.20 Video Display Field 2 Vertical Synchronization End Register (VD\ VSYNE2)

      227
    • 4.12.21 Video Display Counter Reload Register (VDRELOAD)

      228
    • 4.12.22 Video Display Display Event Register (VDDISPEVT)

      229
    • 4.12.23 Video Display Clipping Register (VDCLIP)

      230
    • 4.12.24 Video Display Default Display Value Register (VDDEFVAL)

      231
    • 4.12.25 Video Display Vertical Interrupt Register (VDVINT)

      233
    • 4.12.26 Video Display Field Bit Register (VDFBIT)

      234
    • 4.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)\

      235
    • 4.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)\

      237
  • 4.13 Video Display Registers Recommended Values

    239
  • 4.14 Video Display FIFO Registers

    241
• Chapter 5: General Purpose I/O Operation

  242
  • 5.1 GPIO Registers

    243
    • 5.1.1 Video Port Peripheral Identification Register (VPPID)

      244
    • 5.1.2 Video Port Peripheral Control Register (PCR)

      245
    • 5.1.3 Video Port Pin Function Register (PFUNC)

      247
    • 5.1.4 Video Port Pin Direction Register (PDIR)

      249
    • 5.1.5 Video Port Pin Data Input Register (PDIN)

      252
    • 5.1.6 Video Port Pin Data Output Register (PDOUT)

      254
    • 5.1.7 Video Port Pin Data Set Register (PDSET)

      256
    • 5.1.8 Video Port Pin Data Clear Register (PDCLR)

      258
    • 5.1.9 Video Port Pin Interrupt Enable Register (PIEN)

      260
    • 5.1.10 Video Port Pin Interrupt Polarity Register (PIPOL)

      262
    • 5.1.11 Video Port Pin Interrupt Status Register (PISTAT)

      264
    • 5.1.12 Video Port Pin Interrupt Clear Register (PICLR)

      266
• Chapter 6: VCXO Interpolated Control Port

  268
  • 6.1 Overview

    269
  • 6.2 Interface

    270
  • 6.3 Operational Details

    270
  • 6.4 Enabling VIC Port

    272
  • 6.5 VIC Port Registers

    272
    • 6.5.1 VIC Control Register (VICCTL)

      273
    • 6.5.2 VIC Input Register (VICIN)

      275
    • 6.5.3 VIC Clock Divider Register (VICDIV)

      276
• Appendix A: Video Port Configuration Examples

  277
  • A.1 Example 1: Noncontinuous Frame Capture for 525/60 Format

    278
  • A.2 Example 2: Noncontinuous Frame Display for 525/60 Format

    286
• Index

  297