Manuale UtenteSommarioSpartan-3A DSP FPGA Family:1Data Sheet1Introduction and Ordering Information3Introduction3Spartan-3A and Spartan-3A DSP FPGA Differences3Features3Architectural Overview4Configuration4I/O Capabilities4Package Marking6Ordering Information6Standard Packaging6Pb-Free Packaging6Revision History7Functional Description9Introduction9Revision History9DC and Switching Characteristics11DC Electrical Characteristics11Absolute Maximum Ratings11Power Supply Specifications12General Recommended Operating Conditions12General DC Characteristics for I/O Pins13Quiescent Current Requirements14Single-Ended I/O Standards15Differential I/O Standards17External Termination Requirements for Differential I/O19Device DNA Data Retention, Read Endurance19Switching Characteristics20Software Version Requirements20I/O Timing22Timing Measurement Methodology31Using IBIS Models to Simulate Load Conditions in Application33Simultaneously Switching Output Guidelines33Configurable Logic Block (CLB) Timing36Clock Buffer/Multiplexer Switching Characteristics37Block RAM Timing38DSP48A Timing39Digital Clock Manager (DCM) Timing41Delay-Locked Loop (DLL)41Digital Frequency Synthesizer (DFS)43Phase Shifter (PS)44Miscellaneous DCM Timing44DNA Port Timing45Suspend Mode Timing46Configuration and JTAG Timing47General Configuration Power-On/Reconfigure Timing47Configuration Clock (CCLK) Characteristics48Master Serial and Slave Serial Mode Timing50Slave Parallel Mode Timing51Serial Peripheral Interface (SPI) Configuration Timing52Byte Peripheral Interface (BPI) Configuration Timing54IEEE 1149.1/1553 JTAG Test Access Port Timing56Revision History57Pinout Descriptions59Introduction59Pin Types59Package Pins by Type60Package Thermal Characteristics61CS484: 484-Ball Chip-Scale Ball Grid Array62Pinout Table62User I/Os by Bank68Footprint Migration Differences68CS484 Footprint69Left Half of Package (top view)69Right Half of CS484 Package (top view)70FG676: 676-Ball Fine-Pitch Ball Grid Array71XC3SD1800A FPGA71Pinout Table71User I/Os by Bank80FG676 Footprint - XC3SD1800A FPGA81XC3SD3400A FPGA83Pinout Table83User I/Os by Bank92FG676 Footprint - XC3SD3400A FPGA93Footprint Migration Differences95Migration Recommendations96Revision History97Dimensioni: 2,7 MBPagine: 98Language: EnglishApri il manuale