Hitachi H8/3692 ユーザーズマニュアル

Rev. 71, 07/01, page 85 of 372

FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.

7

PDWND

0

R/W

Power-Down Disable

When this bit is 0 and a transition is made to the subactive
mode, the flash memory enters the power-down mode.
When this bit is 1, the flash memory remains in the normal
mode even after a transition is made to the subactive
mode.

6

5

4

3

2

1

0

—

—

—

—

—

—

—

0

0

0

0

0

0

0

—

—

—

—

—

—

—

Reserved

These bits are always read as 0, and cannot be modified.

FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR1,
and FLPWCR.

7

FLSHE

0

R/W

Flash Memory Control Register Enable

Flash memory control registers can be accessed when this
bit is set to 1. Flash memory control registers cannot be
accessed when this bit is set to 0.

6

5

4

3

2

1

0

—

—

—

—

—

—

—

0

0

0

0

0

0

0

—

—

—

—

—

—

—

Reserved

These bits are always read as 0, and cannot be modified.