Hitachi H8/3692 ユーザーズマニュアル

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Rev. 1.0, 07/01, Page 
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Figure 11-8   Clear Timing by TMRIV Input ...............................................................................146
Figure 11-9   Pulse Output Example.............................................................................................147
Figure 11-10   Example of Pulse Output Synchronized to TRGV Input.......................................148
Figure 11-11   Contention between TCNTV Write and Clear ......................................................149
Figure 11-12   Contention between TCORA Write and Compare Match .....................................149
Figure 11-13   Internal Clock Switching and TCNTV Operation.................................................150
Section 12   Timer W
Figure 12-1   Timer W Block Diagram.........................................................................................153
Figure 12-2   Free-Running Counter Operation ............................................................................162
Figure 12-3   Periodic Counter Operation.....................................................................................163
Figure 12-4   0 and 1 Output Example(TOA = 0, TOB = 1).........................................................163
Figure 12-5   Toggle Output Example (TOA = 0, TOB = 1) ........................................................164
Figure 12-6   Toggle Output Example (TOA = 0, TOB = 1) ........................................................164
Figure 12-7   Input Capture Operating Example...........................................................................165
Figure 12-8   Buffer Operation Example (Input Capture).............................................................165
Figure 12-9   PWM Mode Example (1) ........................................................................................166
Figure 12-10   PWM Mode Example (2) ......................................................................................167
Figure 12-11   Buffer Operation Example (Output Compare) ......................................................167
Figure 12-12   PWM Mode Example
               (TOB=0, TOC=0, TOD=0: initial output values are set to 0) ................................168
Figure 12-13   PWM Mode Example
               (TOB=1, TOC=1,and TOD=1: initial output values are set to 1) ..........................169
Figure 12-14   Count Timing for Internal Clock Source...............................................................170
Figure 12-15   Count Timing for External Clock Source..............................................................170
Figure 12-16   Output Compare Output Timing ...........................................................................171
Figure 12-17   Input Capture Input Signal Timing .......................................................................171
Figure 12-18   Timing of Counter Clearing by Compare Match...................................................172
Figure 12-19   Buffer Operation Timing (Compare Match) .........................................................172
Figure 12-20   Buffer Operation Timing (Input Capture) .............................................................173
Figure 12-21   Timing of IMFA to IMFD Flag Setting at Compare Match ..................................173
Figure 12-22   Timing of IMFA to IMFD Flag Setting at Input Capture......................................174
Figure 12-23   Timing of Status Flag Clearing by the CPU..........................................................174
Figure 12-24   Contention between TCNT Write and Clear .........................................................175
Figure 12-25   Internal Clock Switching and TCNT Operation....................................................176
Section 13   Watchdog Timer
Figure 13-1   Block Diagram of WDT ..........................................................................................177
Figure 13-2   Watchdog Timer Operation Example......................................................................180
Section 14   Serial Communication Interface3 (SCI3)
Figure 14-1   Block Diagram of SCI3...........................................................................................182
Figure 14-2   Data Format in Asynchronous Communication ......................................................195