Hitachi H8/3692 ユーザーズマニュアル
Rev. 1.0, 07/01, page 173 of 372
GRA, GRB
TCNT
Input capture
signal
signal
φ
GRC, GRD
N
M
M
N+1
N
N
N+1
Figure 12-20 Buffer Operation Timing (Input Capture)
12.5.6
Timing of IMFA to IMFD Flag Setting at Compare Match
If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register. The compare match signal is generated in the last state in which the values match (when
TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a
general register, the compare match signal is generated only after the next TCNT clock pulse is
input. Figure 12-21 shows the timing of the IMFA to IMFD flag setting at compare match.
corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general
register. The compare match signal is generated in the last state in which the values match (when
TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a
general register, the compare match signal is generated only after the next TCNT clock pulse is
input. Figure 12-21 shows the timing of the IMFA to IMFD flag setting at compare match.
GRA to GRD
TCNT
TCNT input
clock
clock
φ
N
N
N+1
Compare
match signal
match signal
IMFA to IMFD
IRRTW
Figure 12-21 Timing of IMFA to IMFD Flag Setting at Compare Match