Hitachi H8/3692 ユーザーズマニュアル
Rev. 1.0, 07/01, page 190 of 372
14.3.8
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 13-2
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 13-3 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 13-2 and 13-3 are values in active (high-
speed) mode. Table 13-4 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 13-4 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of
SMR in asynchronous mode. Table 13-3 shows the maximum bit rate for each frequency in
asynchronous mode. The values shown in both tables 13-2 and 13-3 are values in active (high-
speed) mode. Table 13-4 shows the relationship between the N setting in BRR and the n setting in
bits CKS1 and CKS0 of SMR in clocked synchronous mode. The values shown in table 13-4 are
values in active (high-speed) mode. The N setting in BRR and error for other operating
frequencies and bit rates can be obtained by the following formulas:
[Asynchronous Mode]
N =
φ
64
×
2
2n–1
×
B
×
10
6
– 1
Error(%) = - 1
×
100
φ
×
10
6
(N + 1)
×
B
×
64
×
2
2n–1
[Clocked Synchronous Mode]
N =
φ
8
×
2
2n–1
×
B
×
10
6
– 1
Note: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0
≤
N
≤
255)
φ
: Operating frequency (MHz)
n: CKS1 and CKS0 settings in SMR (0
≤
n
≤
3)