Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, page 195 of 372

Figure 14-2 shows the general format for asynchronous serial communication. One character (or
frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or
low level), and finally stop bits (high level). Inside the SCI, the transmitter and receiver are
independent units, enabling full-duplex. Both the transmitter and the receiver also have a double-
buffered structure, so data can be read or written during transmission or reception, enabling
continuous data transfer.

LSB

Start
bit

MSB

Idle state
(mark state)

Stop bit

Transmit/receive data

1

1

Serial
data

Parity
bit

1 bit

1 or
2 bits

7 or 8 bits

1 bit,
or none

One unit of transfer data (character or frame)

Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK3 pin can be selected as the SCI’s serial clock, according to the setting of the COM bit in
SMR and the CKE0 and CKE1 bits in SCR3. When an external clock is input at the SCK3 pin, the
clock frequency should be 16 times the bit rate used.

When the SCI is operated on an internal clock, the clock can be output from the SCK3 pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 14-3.

0

1 frame or frame

D0

D1

D2

D3

D4

D5

D6

D7

0/1

1

1

Clock

Serial data