Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, page 206 of 372

Figure 14-12 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.

1.

 

The SCI performs internal initialization synchronous with a synchronization clock input or
output, starts receiving data.

2.

 

The SCI stores the receive data in RSR.

3.

 

If an overrun error occurs (when reception of the next data is completed while the RDRF flag
in SSR is still set to 1), the OER bit in SSR is set to 1. If the RIE bit in SCR3 is set to 1 at this
time, an ERI interrupt request is generated, receive data is not transferred to RDR, and the
RDRF flag remains to be set to 1.

4.

 

If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR3 is set to 1 at this time, an RXI interrupt request is
generated.

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 14-13 shows a sample flow
chart for serial data reception.

Synchronization
clock

Serial
data

1 frame

1 frame

Bit 0

Bit 7

Bit 7

Bit 0

Bit 1

Bit 6

Bit 7

RDRF

OER

LSI
operation

User 
processing

RXI interrupt request generated

RDR data read

RDRF flag
cleared 
to 0

RXI interrupt
request
generated

ERI interrupt request 
generated by 
overrun error

Overrun error 
processing

RDR data has 
not been read 
(RDRF = 1)