Hitachi H8/3692 ユーザーズマニュアル
Rev. 1.0, 07/01, page 227 of 372
15.3.3
I
2
C Bus Mode Register (ICMR)
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
first, performs master mode wait control, and selects the transfer bit count.
Bit
Bit Name
Initial Value R/W
Description
7
MLS
0
R/W
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
2
C bus format is used.
6
WAIT
0
R/W
Wait Insertion Bit
In master mode with the I
2
C bus format, this bit selects
whether to insert a wait after data transfer except the
acknowledge bit. When WAIT is set to 1, after the fall of the
clock for the final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait
inserted.
acknowledge bit. When WAIT is set to 1, after the fall of the
clock for the final data bit, low period is extended for two
transfer clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with no wait
inserted.
The setting of this bit is invalid in slave mode with the I
2
C
bus format or with the clocked synchronous serial format.
5
4
4
1
1
1
Reserved
These bits are always read as 1, and cannot be modified.
3
BCWP
1
R/W
BC Write Protect
This bit controls the BC2 to BC0 modifications. When
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial mode,
BC should not be modified.
modifying BC2 to BC0, this bit should be cleared to 0 and
use the MOV instruction. In clock synchronous serial mode,
BC should not be modified.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
When writing, settings of BC2 to BC0 are invalid.