Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, page 234 of 372

The I

2

C bus interface can communicate either in I

2

C bus mode or clocked synchronous serial mode

by setting FS in SAR.

Figure 15-3 shows the I

2

C bus formats. Figure 15-4 shows the I

2

C bus timing. The first frame

following a start condition always consists of 8 bits.

S

SLA

R/

A

DATA

A

A/

P

1

1

1

1

n

7

1

m

(a)  I

2

C bus format (FS = 0)

(b)  I

2

C bus  format (Start condition retransmission, FS = 0)

n: Transfer bit count 
     (n = 1 to 8)

m: Transfer frame count 
      (m 

≥

 1)

S

SLA

R/

A

DATA

1

1

1

n1

7

1

m1

S

SLA

R/

A

DATA

A/

P

1

1

1

n2

7

1

m2

1

1

1

A/

n1 and n2: Transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: Transfer frame count (m1 and m2 

≥

 1)

1

1

SDA

SCL

S

1-7

SLA

8

R/

9

A

1-7

DATA

8

9

1-7

8

9

A

DATA

P

A

S: 

Start condition. The master device drives SDA from high to low while SCL is high.

SLA: Slave 

address

R/

W:  Indicates the direction of data transfer: from the slave device to the master device when

R/

W is 1, or from the master device to the slave device when R/W is 0.

A:

Acknowledge. The receive device drives SDA to low.

DATA: Transfer data