Hitachi H8/3692 ユーザーズマニュアル
Rev. 1.0, 07/01, page 270 of 372
V
CC
Vreset
V
SS
OVF
PSS-reset
signal
signal
Internal reset
signal
signal
PSS counter starts
Reset released
131,072 cycles
Figure 17-3 Operational Timing of LVDR
Interrupt by Low Voltage Detect (LVDI) :
Figure 17-4 shows the timing of LVDI functions. LVDI enters the module-standby state when
power is first supplied. To operate the LVDI, set LVDE in LVDCR to 1, wait for 10
power is first supplied. To operate the LVDI, set LVDE in LVDCR to 1, wait for 10
µ
s until the
reference voltage and the low-voltage-detection power supply have stabilized, then set LVDDE
and LVDUE in LVDCR to 1.
and LVDUE in LVDCR to 1.
When the power-supply voltage falls below the Vint potential (the potential specified by VLDSEL
in LVDCR), LVDI clears the
in LVDCR), LVDI clears the
LVDINT signal to 0. If LVDDE is 1 at this time, LVDDF is set to 1
and an IRQ0 interrupt request is simultaneously generated. When the power-supply voltage rises
above the Vint potential, LVDI sets the
above the Vint potential, LVDI sets the
LVDINT signal to 1. If LVDUE is 1 at this time, LVDUF
is set to 1 and an IRQ0 interrupt request is simultaneously generated.