Hitachi H8/3692 ユーザーズマニュアル
Rev. 1.0, 07/01, page 7 of 372
Section 2 CPU
This LSI has an H8/300H CPU with an internal 32-bit architecture that is upword-compatible with
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space.
•
Upward-compatible with H8/300 CPUs
Can execute H8/300 CPUs object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added.
•
General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers and eight 16-bit
registers, or eight 32-bit registers
registers, or eight 32-bit registers
•
Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
•
Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:24,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
•
64-kbyte address space
•
High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract
: 2 state
8
×
8-bit register-register multiply
: 14 states
16 ÷ 8-bit register-register divide
: 14 states
16
×
16-bit register-register multiply : 22 states
32 ÷ 16-bit register-register divide
: 22 states
•
Power-down state
Transition to power-down state by SLEEP instruction
CPU30H2D0000_000020010700