Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, page 50 of 372

When the 

RES pin goes low, all processing halts and this LSI enters the reset. The internal state of

the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure
that this LSI is reset at power-up, hold the 

RES pin low until the clock pulse generator output

stabilizes. To reset the chip during operation, hold the 

RES pin low for at least 10 system clock

cycles. When the 

RES pin goes high after being held low for the necessary time, this LSI starts

reset exception handling. The reset exception handling sequence is shown in figure 3-1.

The reset exception handling sequence is as follows. However, for the reset exception handling
sequence of the product with on-chip power-on reset circuit, refer to section 19, Power-on Reset
and Low-Voltage Detection Circuits.

1. Set the I bit in the condition code register (CCR) to 1.

2. The CPU generates a reset exception handling vector address (from H'0000 to H'0001), the

data in that address is sent to the program counter (PC) as the start address, and program
execution starts from that address.

As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts.

NMI interrupt is requested by input signal edge to pin 

NMI. This interrupt is detected by either

rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.

NMI is the highest-priority interrupt, and can always be accepted without depending on the  I
bit value in CCR.

IRQ3 to IRQ0 interrupts are requested by input signals to pins 

IRQ3 to IRQ0. These four

interrupts are given different vector addresses, and are detected individually by either rising
edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in
IEGR1.

When pins 

IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal

edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
These interrupts can be masked by setting bits IEN3 to IEN0 in IENR1.