Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, page 54 of 372

Vector fetch

ø

Internal

address bus

Internal read

signal

Internal write

signal

(2)

Internal data bus

(16 bits)

Interrupt 

request signal

(9)

(1)

Internal

processing

Prefetch instruction of 

interrupt-handling routine

(1)  Instruction prefetch address (Instruction is not executed.  Address is saved as PC contents, becoming return address.)

(2)(4)  Instruction code (not executed)

(3)  Instruction prefetch address (Instruction is not executed.)

(5)  SP – 2

(6)  SP – 4

(7)  CCR

(8)  Vector address

(9)  Starting address of interrupt-handling routine (contents of vector)

(10)  First instruction of interrupt-handling routine

(3)

(9)

(8)

(6)

(5)

(4)

(1)

(7)

(10)

Stack access

Internal

processing

Instruction 

prefetch

Interrupt level 

decision and wait for 

end of instruction

Interrupt is 

accepted