Hitachi H8/3692 ユーザーズマニュアル

Rev. 1.0, 07/01, page 60 of 372

BDR (BDRH, BDRL) is a 16-bit read/write register that sets the data for generating an address
break interrupt.  BDRH is compared with the upper 8-bit data bus.  BDRL is compared with the
lower 8-bit data bus.  When memory or registers are accessed by byte, the upper 8-bit data bus is
used for even and odd addresses in the data transmission.  Therefore, comparison data must be set
in BDRH for byte access.  For word access, the data bus used depends on the address.  See section
4.1.1, Address Break Control Register, for details. The initial value of this register is undefined.

When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the
combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR,
the address break function generates an interrupt request to the CPU.  When the interrupt request
is accepted, interrupt exception handling starts after the instruction being executed ends.  The
address break interrupt is not masked by the I bit in CCR of the CPU.

Figures 4-2 show the operation examples of the address break interrupt setting.

NOP

instruc-

tion

prefetch

Register setting
•  ABRKCR = H'80
•  BAR = H'025A

Program

0258
025A
025C
0260
0262
   :

*

NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
   :

0258

Address 
bus

φ

Interrupt 
request

025A

025C

025E

SP-2

SP-4

NOP

instruc-

tion

prefetch

MOV

instruc-

tion 1

prefetch

MOV

instruc-

tion 2

prefetch

Internal

processing

Stack save

Interrupt acceptance

Underline indicates the address 
to be stacked.

When the address break is specified in instruction execution cycle