Panasonic MN101C77C ユーザーズマニュアル

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Chapter 2 CPU Basics

Bus Interface

2-3

Bus Interface

2-3-1

Bus Controller

The MN101C series provides separate buses to the internal memory and internal peripheral circuits to

reduce bus line loads and thus realize faster operation.

There are three such buses: ROM bus, RAM bus, and peripheral expansion bus (I/O bus). They connect

to the internal ROM, internal RAM, and internal peripheral circuits respectively. The bus control block

controls the parallel operation of instruction read and data access. A functional block diagram of the bus

controller is given below.

Figure 2-3-1 Functional Block Diagram of the Bus Controller

Instruction

queue

Program address

Operand address

Interrupt

control

Interrupt

bus

Memory control register

Memory mode setting
Bus access (wait)
control

Bus
arbitor

Peripheral

extension bus

Internal

peripheral functions

RAM bus

Internal RAM

ROM bus

Address decode

Bus controller

Internal ROM