Intel L5530 AT80602002937AB ユーザーズマニュアル
製品コード
AT80602002937AB
Intel
®
Xeon
®
Processor 5500 Series Datasheet, Volume 1
7
6-16 PCIConfigRd() Response Definition .................................................................... 112
6-17 PCIConfigWr() Device/Function Support ............................................................. 113
6-18 PCIConfigWr() Response Definition .................................................................... 114
6-19 Mailbox Command Summary ............................................................................ 115
6-20 Counter Definition ........................................................................................... 116
6-21 Machine Check Bank Definitions ........................................................................ 118
6-22 ACPI T-state Duty Cycle Definition ..................................................................... 119
6-23 MbxSend() Response Definition ......................................................................... 121
6-24 MbxGet() Response Definition ........................................................................... 122
6-25 Domain ID Definition ....................................................................................... 124
6-26 Multi-Domain Command Code Reference ............................................................ 124
6-27 Completion Code Pass/Fail Mask........................................................................ 124
6-28 Device Specific Completion Code (CC) Definition.................................................. 125
6-29 Originator Response Guidelines ......................................................................... 125
6-30 Error Codes and Descriptions ............................................................................ 127
6-31 PECI Client Response During Power-Up (During ‘Data Not Ready’) ......................... 127
6-32 Power Impact of PECI Commands versus C-states ............................................... 129
6-33 PECI Client Response During S1 ........................................................................ 129
7-1
6-17 PCIConfigWr() Device/Function Support ............................................................. 113
6-18 PCIConfigWr() Response Definition .................................................................... 114
6-19 Mailbox Command Summary ............................................................................ 115
6-20 Counter Definition ........................................................................................... 116
6-21 Machine Check Bank Definitions ........................................................................ 118
6-22 ACPI T-state Duty Cycle Definition ..................................................................... 119
6-23 MbxSend() Response Definition ......................................................................... 121
6-24 MbxGet() Response Definition ........................................................................... 122
6-25 Domain ID Definition ....................................................................................... 124
6-26 Multi-Domain Command Code Reference ............................................................ 124
6-27 Completion Code Pass/Fail Mask........................................................................ 124
6-28 Device Specific Completion Code (CC) Definition.................................................. 125
6-29 Originator Response Guidelines ......................................................................... 125
6-30 Error Codes and Descriptions ............................................................................ 127
6-31 PECI Client Response During Power-Up (During ‘Data Not Ready’) ......................... 127
6-32 Power Impact of PECI Commands versus C-states ............................................... 129
6-33 PECI Client Response During S1 ........................................................................ 129
7-1