Mitsubishi Electronics Q172DCPU ユーザーズマニュアル

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APP - 35 
APPENDICES 
 
APPENDIX 4.3 Differences of each mode 
(1)   Motion SFC 
 
Table 4.9 Differences in Motion SFC mode 
Item Q173DCPU/Q172DCPU 
Q173HCPU/Q172HCPU 
Motion SFC program executing flag 
X, Y, M, B, U \G — 
Operation control/transition control usable device 
(Word device) 
D, W, U \G, SD, #, FT 
D, W, Special D, #, FT 
Operation control/transition control usable device 
(Bit device) 
X, PX, Y, PY, M, U \G . , B, F, SM 
X, PX, Y, PY, M, L, B, F, Special M 
 
 
(2)   Virtual mode 
 
Table 4.10 Differences in Virtual mode 
Item Q173DCPU/Q172DCPU 
Q173HCPU/Q172HCPU 
M4640 to M4687
M5440 to M5487
Internal relay/ 
Data register 
D1120 to D1239 
Device area of 9 axes or more is usable as user 
devices in the Q172DCPU. 
Device area of 9 axes or more is unusable in the 
Q172HCPU. 
Clutch status 
Optional device 
(Set for M2160 to M2223 are also usable.) 
M2160 to M2223 
Cam axis command signals 
(Cam/ball screw switching 
command) 
Optional device 
(Set for M5488 to M5519 are also usable.) 
M5488 to M5519 
Smoothing clutch complete signals 
Optional device 
(Set for M5520 to M5583 are also usable.) 
M5520 to M5583 
Real mode axis information register 
SD500, SD501 
D790, D791 
D0 to D8191 
D800 to D3069, D3080 to D8191 
W0 to W1FFF 
W0 to W1FFF 
#0 to #7999 
— 
Indirect setting devices of 
mechanical system program 
(Word device) 
U \G10000 to U \G(10000 + p –1 ) 
(Note-1)
 
— 
X0 to X1FFF 
X0 to X1FFF 
Y0 to Y1FFF 
Y0 to Y1FFF 
M0 to M8191 
M/L0 to M/L8191 
— 
M9000 to M9255 
B0 to B1FFF 
B0 to B1FFF 
F0 to F2047 
F0 to F2047 
Indirect setting devices of 
mechanical system program 
(Bit device) 
U \G10000.0 to U \G(10000 + p –1 ).F 
(Note-1)
— 
Speed change ratio of speed 
change gear 
Upper limit value : 0 to 65535 
Lower limit value : 0 to 65535 
Upper limit value : 1 to 10000 
Lower limit value : 1 to 10000 
Permissible droop pulse value of 
output module 
1 to 1073741824 [PLS] 
1 to 65535[
∗100PLS] 
 
(Note-1) : "p" indicates user setting area points of Multiple CPU high speed transmission area in each CPU. 
 
 
POINT 
 
Refer to Chapter 2 for number of user setting area points of Multiple CPU high 
speed transmission area.