Avaya 03-300430 ユーザーズマニュアル

1

FAIL

This error means the Tone-Clock circuit framing verification firmware 
reports an error in the clock synchronization signal coming into this port 
network.

1. If the Tone-Clock circuit reporting the problem is a master clock, then 

the system synchronization reference is providing a bad timing 
source. See 

on page 2143 or 

on page 2128 to change the system 

synchronization reference.

2. If the Tone-Clock circuit is a slave clock, then the EI to which it is 

listening is providing a bad timing source. Follow the diagnostic 
procedures specified for TDM-CLK Error Code 2305.

3.

 / 

: If no problem can be found with the incoming 

synchronization signal, replace the IPSI or Tone-Clock circuit pack. 
See 

2

FAIL

This error indicates that Tone-Clock circuit has inaccurately detected loss of 

signal on the incoming synchronization timing source.

4

8

FAIL

The local oscillator on the Tone-Clock circuit failed.

16
32

FAIL

The circuitry on the Processor/Tone-Clock circuit used to detect 
synchronization timing errors has failed.

1. Errors 2, 4, 8, 16, and 32 indicate that there is poor synchronization 

between port networks and external facilities. It may be noticeable to 
the customer in the form of errors in data communications. The 
Tone-Clock circuit is defective. See 

64

FAIL

This message is only sent when an uplink message has reported the loss 
of valid synchronization timing information coming into this port network. It 
has been reported in TDM-CLK Error Log entries; one or more of 1025, 
1281, 1537, 2049 and 2305.

1. Resolve the errors indicated. No separate corrective action is 

required.

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