Intel EP80579 ユーザーズマニュアル

Intel

®

 EP80579 Software for Security Applications on Intel

®

 QuickAssist Technology

PG

August 2009

12

Order Number: 320183-004US

No updates in this release. 

The Intel

®

 EP80579 Integrated Processor is a System On a Chip (SOC), integrating the 

Intel

®

 Architecture core processor, the Integrated Memory Controller Hub (IMCH) and 

the Integrated I/O Controller Hub (IICH) all on the same die. In addition, it has 

integrated Intel

®

 QuickAssist Technology, which provides acceleration of cryptographic 

and packet processing. It also includes three gigabit Ethernet MACs, TDM interfaces, 

and PCI Express. See 

 for details. 

• As an SOC, the EP80579 integrates the processor and chipset as follows:

— The IA-32 core is based on the Intel

®

 

Pentium

®

 

M processor, and runs at 600-

1200MHz, with a 256 Kilobyte 2-way level 2 (L2) cache.

— The IMCH provides the main path to memory for the IA core and all peripherals 

that perform coherent I/O (for example, the PCI express, the IICH, as well as 

transactions from the Acceleration and I/O Complex to coherent memory).

— The IICH provides a set of PC platform-compatible I/O devices that include two 

SATA 1.0/2.0, two USB 1.1/2.0 host controller supporting two USB ports, and 

two serial 16550 compatible UART interfaces.

• The  Intel

®

 QuickAssist Technology components, housed in the Acceleration and I/O 

Complex (AIOC), are as follows:

— The Security Services Unit (SSU) provides acceleration of cryptographic 

processing for most common symmetric cryptography (cipher algorithms such 

as AES, 3DES, DES, (A)RC4, and messages digest/hash functions such as MD5, 

SHA-1, SHA-2, HMAC, etc.); asymmetric cryptography (modular 

exponentiation to support public key encryption such as RSA, Diffie-Hellman, 

DSA); and true random number generation.

— The Acceleration Services Unit (ASU) includes packet processing acceleration 

engines.

• Other components within the AIOC include:

— Three Gigabit Ethernet (GbE) media access controllers (MACs).
— Three High Speed Serial (HSS) interfaces that support up to 12 T1/E1 TDM 

interfaces. These interfaces are driven by a Programmable I/O Unit (PIU). The 

PIU is not part of the ASU. In 

, the PIU is shown as the TDM 

Interface block.

— Although not shown explicitly in 

, the AIOC also contains logic to allow 

agents to access on-chip SRAM and external DRAM. Based on registers which 

can be configured in the BIOS, this logic routes requests to external DRAM 

either directly to the memory controller (to access non-coherent DRAM, or 

NCDRAM); or through the IMCH for coherency with the IA processor’s L2 cache 

(to access Coherent DRAM, or CDRAM). There is also a ring controller, which