Samsung M8 ユーザーズマニュアル

Spinpoint M8 Product Manual REV 2.3

5.2.2.1 The Host Interface Control Block

The SATA Disk Controller provides direct interface to an SATA bus. It is compatible with ATA 7 Specs. It
provides a means for the host to access the Task File registers used to control the transfer of data between
host memory and the disk drive.

The SATA Host Interface Control block can be programmed to execute various host read/write commands either
completely automatically without any DSP intervention, semi-automatically with minimal DSP intervention, or
manually with the aid of the DSP.

The Disk Controller has significant advances in ATA automation. The highlights of ATA automation includes:

 Automatic data transfer management for multi-sector Read/Write commands without DSP intervention.
 Automatic execution of read commands (Auto-Read command execution) for cached data in the buffer by

matching the first sector.

 Automatic Task File registers updates during automatic multi-sector transfers.
 Automatic NCQ queue tag validation

Spinpoint M8 supports PIO, DMA, and FPDMA data transfers. The supported DMA type transfers include multi-
word (MWDMA) and synchronous Ultra DMA (UDMA) transfers.

The bus emulates automatically switched

between 16- and 8-bit mode while performing Read Long and Write Long commands at the time of ECC byte
transfers.

Additional functionality is provided in the Host Interface Block by the following features:

    Programmable transfer length for automatic ECC byte transfer on the AT bus.
    Support of both LBA and CHS Task File registers formats.
    Automatic detection of both the Software Reset and COMRESET.
    Support for PIO modes 0 through 4.
    Support for multiword DMA modes 0 through 2.
    Support for multiword DMA modes 0 through 2. Support for synchronous DMA (UDMA) transfer mode

0 through 7. (Mode 7 is referring to 150 MB/S)

 Support for First Party DMA (FDMA) for NCQ commands.

5.2.2.2 The Buffer Control Block

The Buffer Control block manages the flow of data into and out of the buffer. Significant automation allows buffer
activity to take place automatically during read/write operations between the host and the disk. This automation
works together with automation within the Host Interface Control and Disk Control blocks to provide more
bandwidth for the local microprocessor to perform non-data flow functions.

The buffer control circuitry keeps track of buffer full and empty conditions and automatically works with the Disk
Control block to stop transfers to or from the disk when necessary. In addition, transfers to or from the host are
automatically stopped or started based on buffer full or empty status.

A prioritized five ports architecture is implemented.

All ports, except the refresh port, utilize 22-bit buffer address

pointers.

The data path to the buffer RAM can be configured as 16-bit path in ATA mode.