Seagate Ultra 320 ユーザーズマニュアル
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Parallel SCSI Interface Product Manual, Rev. A )
SE SCSI devices with data transfer rates up to and including Fast-20 shall use the measurement points
defined in Section 9 of ANSI standard SPI-4, for the measurement of the timing values. The rise and fall times
for the SE REQ/ACK signals shall be nominally the same as for the SE Data, DB(P_CRCA), and DB(P1) sig-
nals.
defined in Section 9 of ANSI standard SPI-4, for the measurement of the timing values. The rise and fall times
for the SE REQ/ACK signals shall be nominally the same as for the SE Data, DB(P_CRCA), and DB(P1) sig-
nals.
SE Fast-20 timing measurement points shall apply even if a slower transfer rate is negotiated.
SE SCSI devices are not capable of Fast-40 and Fast-80 data transfer rates. LVD circuits are required for
these faster transfer rates.
these faster transfer rates.
2.6.3
LVD measurement points
When transferring data using ST LVD phases, LVD SCSI devices shall use the measurement points defined in
Section 9 Figure 60 of ANSI standard SPI-5, for the measurement of timing values. When transferring data
using DT DATA phases, LVD SCSI devices shall use the measurement points defined in Section 9 Figure 61 of
SPI-5, for the measurement of timing values. When transferring data using DT DATA phases LVD SCSI
devices using paced transfers shall use the measurement points defined in Section 9 Figure 62 of SPI-5 for the
measurement of the timing values. The rise and fall times for the LVD REQ/ACK signals shall be nominally the
same as for the LVD Data, P_CRCA, and DP-1 signals.
Section 9 Figure 60 of ANSI standard SPI-5, for the measurement of timing values. When transferring data
using DT DATA phases, LVD SCSI devices shall use the measurement points defined in Section 9 Figure 61 of
SPI-5, for the measurement of timing values. When transferring data using DT DATA phases LVD SCSI
devices using paced transfers shall use the measurement points defined in Section 9 Figure 62 of SPI-5 for the
measurement of the timing values. The rise and fall times for the LVD REQ/ACK signals shall be nominally the
same as for the LVD Data, P_CRCA, and DP-1 signals.
2.7
Clocking methods for data transfers
This manual defines optional methods of latching data from the REQ and ACK signals depending on whether
ST DATA phases or DT DATA phases are being used for information transfers as shown in Figure 5. Data shall
only be latched on the asserting edge of the REQ or ACK signal except in DT DATA phases. When DT DATA
phases are used, data shall be latched on both the asserting edge and the negating edge of the REQ or ACK
signal.
ST DATA phases or DT DATA phases are being used for information transfers as shown in Figure 5. Data shall
only be latched on the asserting edge of the REQ or ACK signal except in DT DATA phases. When DT DATA
phases are used, data shall be latched on both the asserting edge and the negating edge of the REQ or ACK
signal.
Regardless of whether ST or DT transfers are enabled, the negotiated transfer period sets the maximum rate
at which the data is clocked at in megatransfers per second. As a result, the time from rising edge to rising
edge for REQ and ACK signals for the same transfer rate is twice as long for a DT transfer as it is for an ST
transfer. An example of a negotiated transfer period of 25 ns with ST transfers is shown in figure 6. An example
of a negotiated transfer period of 25 ns with DT transfers is shown in Figure 7. For ST and DT synchronous
transfers the clocking signal (i.e., REQ or ACK) occurs when the DATA BUS is in a steady state.
at which the data is clocked at in megatransfers per second. As a result, the time from rising edge to rising
edge for REQ and ACK signals for the same transfer rate is twice as long for a DT transfer as it is for an ST
transfer. An example of a negotiated transfer period of 25 ns with ST transfers is shown in figure 6. An example
of a negotiated transfer period of 25 ns with DT transfers is shown in Figure 7. For ST and DT synchronous
transfers the clocking signal (i.e., REQ or ACK) occurs when the DATA BUS is in a steady state.