Seagate Ultra 320 ユーザーズマニュアル

Parallel SCSI Interface Product Manual, Rev. A )                                       

   37

The receiver skew compensation and clock shifting adjust the timing relationship between the clocking signal 
(i.e., REQ or ACK) and the signals being clocked (e.g., the data bus signals). That adjustment causes the clock 
signal to align with the middle of the signals being clocked when those signals enter the receiver. The receiver 
is then able to the clock signal to latch valid data.

During paced transfers, the clock signal (i.e., REQ or ACK) transitions at the negotiated transfer period. Data is 
qualified by the clock signal and the phase of the P1 signal.

Receiver skew compensation is not defined in this manual.

There are three types of transfer modes:
• Asynchronous
• Synchronous
• Paced

This section provides a brief description of each of these types of transfer modes.

SCSI device ports default to 8-bit asynchronous transfers.

8-bit asynchronous transfers are used for all COMMAND, STATUS, and MESSAGE phases.

ST DATA phases may use 8-bit or 16-bit asynchronous transfers. Asynchronous transfers are not permitted in 
DT DATA phases.

ST DATA phases shall use synchronous transfers when a synchronous transfer agreement is in effect. ST 
DATA phases may use 8-bit or 16-bit synchronous transfers.

DT DATA phases shall use synchronous transfers when a synchronous transfer agreement is in effect. DT 
DATA phases shall only use wide transfers.

Paced transfers shall only be used in DT DATA phases when a paced transfer agreement is in effect. DT 
phases shall only use wide transfers.

Driver

Precomp

SCSI Device

SCSI Device

Cable

and/or

Backplane

Signal

Adjustment

Skew

Compensator

& Clock

Shift

Receiver

Optional