Seagate Ultra 320 ユーザーズマニュアル
72
Parallel SCSI Interface Product Manual, Rev. A
The data invalid state shall have at least one transition of P1 before changing states. The minimum data invalid
time is four transfer periods. This ensures a maximum run length of three cycles for P1. The data invalid state
shall last an even number of transfer periods.
time is four transfer periods. This ensures a maximum run length of three cycles for P1. The data invalid state
shall last an even number of transfer periods.
From the data invalid state, the sending SCSI device port may resume sending data by reversing the phase of
P1 again.
P1 again.
P1 has the same transmit setup and hold time requirements as data and shall always be detected by the
receiving device on the assertion edge of the delayed clocked REQ or ACK signal.
receiving device on the assertion edge of the delayed clocked REQ or ACK signal.
See Figure 10 for examples of how the P1 signal is used to determine when the REQ or ACK transition clocks
valid data.
valid data.
Figure 10. Use of P1 to establish data valid and data invalid states
3.5.3.2.1
Starting pacing transfers at end of training pattern
See Section 3.5.3.1 for the description of starting a data valid state after a training pattern.
3.5.3.2.2
Starting pacing transfers with no training pattern
Before starting the DT DATA IN phase, the SCSI target port shall wait at least two system deskew delays after
the SEL signal is negated before the first assertion of the REQ signal.
the SEL signal is negated before the first assertion of the REQ signal.
The DT DATA IN phase without training starts on the first assertion of REQ if the SEL is not asserted.
The SCSI target port shall begin pacing transfers only after meeting all the following:
• signal restrictions between information transfer phases listed in Section 3.10;
• the signal restrictions between a RESELECTION phase and a DT DATA IN phase listed in Section 3.3.2; or
• the signal restrictions between a SELECTION phase and a DT DATA OUT phase listed in Section 3.2.1.2.
• signal restrictions between information transfer phases listed in Section 3.10;
• the signal restrictions between a RESELECTION phase and a DT DATA IN phase listed in Section 3.3.2; or
• the signal restrictions between a SELECTION phase and a DT DATA OUT phase listed in Section 3.2.1.2.
The SCSI target port shall begin pacing transfers by:
• simultaneously with the assertion of REQ, the SCSI target port shall begin asserting and negating P1 at
• simultaneously with the assertion of REQ, the SCSI target port shall begin asserting and negating P1 at
twice the negotiated transfer period (e.g., 12.5 ns for Fast-160);
• SCSI target port shall assert and negate P1 at least 8 times [e.g., (2 x 6.25 ns) x 8 = 100 ns at Fast-160]; and
• the SCSI target port may establish a data valid state as described in Section 3.5.3.2.
• the SCSI target port may establish a data valid state as described in Section 3.5.3.2.
The DT DATA OUT phase without training starts on the first assertion of REQ if the SEL is not asserted.
DT Data In phase example
DT Data Out phase example
O - Data is valid on indicated transition
X - Data is invalid on indicated transition
X - Data is invalid on indicated transition
P1
X X X X X X OOOOOOOOOO X X X X X X X X X X X X OOOOOO X X X X OOOOOO
REQ
P1
X X X X X X OOOOOOOOOO X X X X OOX X X X X X OOOOOO X X X X OOOOOO
ACK