Intel 31244 PCI-X ユーザーズマニュアル
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7.4.2
PCI Clock Layout Guidelines
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of
0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz. A
typical PCI-X application may require separate clock point-to-point connections, distributed to
each PCI device. Using a low skew clock buffer helps to meet the maximum clock skew
requirements. The clock buffer also provides clock fanout to multiple PCI-X devices. The
recommended clock buffer layouts are specified as follows:
0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz. A
typical PCI-X application may require separate clock point-to-point connections, distributed to
each PCI device. Using a low skew clock buffer helps to meet the maximum clock skew
requirements. The clock buffer also provides clock fanout to multiple PCI-X devices. The
recommended clock buffer layouts are specified as follows:
•
Match each of the PCI clock buffers lengths to within 0.1” to help keep the timing within the
0.5 ns maximum budget.
0.5 ns maximum budget.
•
Use a skew-limited clock buffer with a tight output-to-output skew specification.
•
Keep the distance between the clock lines and other signals at least 25 mils from each other.
•
Keep the distance between the clock line and itself at a minimum of 25 mils apart (for
serpentine clock layout).
serpentine clock layout).