Xilinx ML510 ユーザーズマニュアル

ML510 Dual Processor Hardware

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The ML510 Dual Processor

design hardware includes:

•

PPC440_0:

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DDR2 Interface (512 MB)

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BRAM (64 KB)

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External Memory Controller

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Networking

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UART

–

Interrupt Controller

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GPIO

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EEPROM (IIC and SPI)

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System ACE CF Interface

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PLB Arbiter

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PPC440_1:

–

DDR2 Interface (512 MB)

–

BRAM (64 KB)

–

Networking

–

UART

–

Interrupt Controller

–

PLB Arbiter

Note: Presentation applies to the ML510