Cypress CY7C1163V18 ユーザーズマニュアル
CY7C1161V18, CY7C1176V18
CY7C1163V18, CY7C1165V18
CY7C1163V18, CY7C1165V18
Document Number: 001-06582 Rev. *D
Page 2 of 29
Logic Block Diagram (CY7C1161V18)
Logic Block Diagram (CY7C1176V18)
51
2K x 8 Array
2K x 8 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[7:0]
Re
ad Add. Decode
Read Data Reg.
RPS
WPS
Q
[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
19
8
32
8
NWS
[1:0]
V
REF
W
rite Add. Decode
Write
Reg
16
A
(18:0)
19
51
2K x 8 Array
2K x 8 Array
51
2K x 8 Array
2K x 8 Array
51
2K x 8 Array
2K x 8 Array
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
QVLD
512
K x 9 Array
CLK
A
(18:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
R
ead Add. Decode
Read Data Reg.
RPS
WPS
Q
[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
19
9
36
9
BWS
[0]
V
REF
W
rite Add. Decode
Write
Reg
18
A
(18:0)
19
512
K x 9 Array
512
K x 9 Array
512
K x 9 Array
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF
QVLD