Cypress CY62157EV30 ユーザーズマニュアル
CY62157EV30 MoBL
®
Document #: 38-05445 Rev. *E
Page 2 of 14
Product Portfolio
Product
Range
V
CC
Range (V)
Speed
(ns)
Power Dissipation
Operating I
CC
, (mA)
Standby, I
SB2
(
µA)
f = 1MHz
f = f
max
Min
Typ
Max
Typ
Max
Typ
Max
Typ
Max
CY62157EV30LL
Ind’l/Auto-A
2.2V
3.0
3.6
45
1.8
3
18
25
2
8
Pin Configuration
The following pictures show the 44-pin TSOP II and 48-pin TSOP I pinouts.
1
2
3
4
5
6
7
8
9
2
3
4
5
6
7
8
9
11
14
31
32
36
35
34
33
35
34
33
37
40
39
38
39
38
12
13
13
41
44
43
42
43
42
16
15
29
30
18
17
20
19
27
28
25
26
22
21
23
24
10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A14
A13
A12
A11
A10
A9
A8
NC
DNU
WE
CE2
DNU
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
IO15/A19
IO7
IO14
IO6
IO13
IO5
IO12
IO4
Vcc
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
OE
Vss
CE1
A0
BYTE
Vss
IO15/A19
IO7
IO14
IO6
IO13
IO5
IO12
IO4
Vcc
IO11
IO3
IO10
IO2
IO9
IO1
IO8
IO0
OE
Vss
CE1
A0
A
5
44-Pin TSOP II
Top View
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
17
A
18
A
9
A
10
A
11
A
12
A
15
A
16
A
14
A
13
OE
BHE
BLE
BHE
BLE
CE
WE
IO
0
IO
1
IO
2
IO
3
IO
4
IO
5
IO
6
IO
7
IO
8
IO
9
IO
10
IO
11
IO
12
IO
13
IO
14
IO
15
V
CC
V
CC
V
SS
V
SS
A
8
48-Pin TSOP I (512K x 16 / 1M x 8)
Top View
Notes
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
3. NC pins are not connected on the die.
4. The 44-TSOP II package has only one chip enable (CE) pin.
5. The BYTE pin in the 48-TSOP I package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
4. The 44-TSOP II package has only one chip enable (CE) pin.
5. The BYTE pin in the 48-TSOP I package has to be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and IO8 to IO14 pins are not used (DNU).