Intel 8XC251SA ユーザーズマニュアル
8XC251SA, SB, SP, SQ USER’S MANUAL
5-4
5.2.4
Addressing Modes
The MCS 251 architecture supports the following addressing modes:
•
register addressing: The instruction specifies the register that contains the operand.
•
immediate addressing: The instruction contains the operand.
•
direct addressing: The instruction contains the operand address.
•
indirect addressing: The instruction specifies the register that contains the operand address.
•
displacement addressing: The instruction specifies a register and an offset. The operand
address is the sum of the register contents (the base address) and the offset.
address is the sum of the register contents (the base address) and the offset.
•
relative addressing: The instruction contains the signed offset from the next instruction to
the target address (the address for transfer of control, e.g., the jump address).
the target address (the address for transfer of control, e.g., the jump address).
•
bit addressing: The instruction contains the bit address.
More detailed descriptions of the addressing modes are given in sections 5.3.1, “Data Addressing
Modes," 5.4.1, “Bit Addressing," and 5.5.1, “Addressing Modes for Control Instructions.”
Modes," 5.4.1, “Bit Addressing," and 5.5.1, “Addressing Modes for Control Instructions.”
5.3
DATA INSTRUCTIONS
Data instructions consist of arithmetic, logical, and data-transfer instructions for 8-bit, 16-bit, and
32-bit data. This section describes the data addressing modes and the set of data instructions.
32-bit data. This section describes the data addressing modes and the set of data instructions.
5.3.1
Data Addressing Modes
This section describes the data-addressing modes, which are summarized in two tables: Table 5-3
for the instructions that are native to the MCS 51 architecture, and Table 5-4 for the new data in-
structions in the MCS 251 architecture.
for the instructions that are native to the MCS 51 architecture, and Table 5-4 for the new data in-
structions in the MCS 251 architecture.
NOTE
References to registers R0–R7, WR0–WR6, DR0, and DR2 always refer to the
register bank that is currently selected by the PSW and PSW1 registers (see
section 5.6, “Program Status Words”). Registers in all banks (active and
inactive) can be accessed as memory locations in the range 00H–1FH.
register bank that is currently selected by the PSW and PSW1 registers (see
section 5.6, “Program Status Words”). Registers in all banks (active and
inactive) can be accessed as memory locations in the range 00H–1FH.
Instructions from the MCS 51 architecture access external memory through the
region of memory specified by byte DPXL in the extended data pointer
register, DPX (DR56). Following reset, DPXL contains 01H, which maps the
external memory to region 01:. You can specify a different region by writing to
DR56 or the DPXL SFR. See section 3.3.2, “Dedicated Registers.”
region of memory specified by byte DPXL in the extended data pointer
register, DPX (DR56). Following reset, DPXL contains 01H, which maps the
external memory to region 01:. You can specify a different region by writing to
DR56 or the DPXL SFR. See section 3.3.2, “Dedicated Registers.”