Samsung C8278X ユーザーズマニュアル

 

dst,src 

dst  

←    dst    +    src 

The source operand is added to the destination operand and the sum is stored in the destination. 
The contents of the source are unaffected. Two's-complement addition is performed. 

Set if there is a carry from the most significant bit of the result; cleared otherwise. 

 

Z:  Set if the result is "0"; cleared otherwise. 

 

S:  Set if the result is negative; cleared otherwise. 

 

V:  Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the 

result is of the opposite sign; cleared otherwise. 

 

D:  Always cleared to "0". 

 

H:  Set if a carry from the low-order nibble occurred. 

 

opc 

dst | src 

 

 

2 

4 

02 

r 

r 

 

    

 6 03 

r 

lr 

 

 

 

 

 

 

 

 

 

 

 opc 

src 

dst 

  3 

6 

04 

R 

R 

 

    

 6 05 

R 

IR 

 

 

 

 

 

 

 

 

 

 

 opc 

dst 

src 

  3 

6 

06 

R 

IM 

 

Given:  R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: 

   

ADD R1,R2 

 

→ 

R1    =    15H, R2    =    03H 

   

ADD R1,@R2 

→ 

R1  =  1CH, R2  =  03H 

   

ADD 01H,02H 

→ 

Register 01H  =  24H, register 02H  =  03H 

   

ADD 01H,@02H 

→ 

Register 01H  =  2BH, register 02H  =  03H 

ADD 01H,#25H 

→ 

Register 01H  =  46H 

 

In the first example, destination working register R1 contains 12H and the source working register 
R2 contains 03H. The statement "ADD    R1,R2" adds 03H to 12H, leaving the value 15H in 
register R1.