Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
5-18
Freescale Semiconductor
CDM Registers
5.5.8
CDM Clock Control Sequencer Configuration Register—MBAR + 0x021C
This register contains the configuration that controls the CCS module. The CCS module lets MPC5200B enter deep sleep power down mode
(all clocks stopped).
(all clocks stopped).
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Write 0
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0–6
—
Reserved for future use. Write 0.
7
sys_osc_disable
CDM System Oscillator Disable
bit=1:System Oscillator is disabled. External clock source is required.
bit=0:System Oscillator is enabled. 27–33MHz crystal is being used.
8–31
—
Reserved for future use. Write 0.
Table 5-15. CDM Clock Control Sequencer Configuration Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
Write 0
cc
s_
sleep_en
Reserved
Write 0
ccs
_osc_
sleep_en
W
RESE
T:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Write 0
cc
s_qr
eq
_test
W
RESE
T:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Bit
Name
Description
0–6
—
Reserved for future use. Write 0.
7
ccs_sleep_en
CCS Module Enable
bit=1:CCS enabled.
e300 Core QREQ signal triggers deep sleep cycle.
bit=0:CCS disabled and inactive. No deep sleep mode possible.
Note: This bit should only be set before the processor should go into deep sleep
mode. And it should be reseted after wake up.
mode. And it should be reseted after wake up.
Note: It is not allowed to set this bit if a JTAG debugger or the nap mode should be
used.
used.
8–14
—
Reserved for future use. Write 0.
15
ccs_osc_sleep_en
CCS System Oscillator Disable Control
bit=1:CCS can disable System Oscillator in deep sleep mode.
bit=0:CCS cannot disable System Oscillator in deep sleep mode. Oscillator
remains active.
remains active.