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Interrupt Controller
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-5
correct behavior, the e300 core always completes the core_int before treating the core_smi. In this case, the CPU does not authorize nested 
interrupt at the exception if the ISR set the 603e’s MSR[EE] to support nested interrupt (core_smi and core_int). 
In order to guaranty the assertion of the core_cint when a core_int is pending, the ISR needs to force the re-evaluation of the Peripheral 
Interrupt condition by writing “1” to the Peripheral Status Encoded Pse msb. The ISR has to repeatedly set this bit since the interrupt events 
are indeterministic. Moreover, the Peripheral Interrupt sources directed to core_cint needs to have their priorities to be higher than the LO_int 
Peripheral Interrupt sources. The Interrupt Controller always activates first the pending interrupt having the highest priority. Like for the 
Peripheral Interrupt Group, the ISR needs to set the Main Status Encoded MSe msb to force re-evaluation of the Main Interrupt Condition and 
each Main Interrupt Priority needs to be properly programmed.
7.2.4
Interrupt Controller Registers
The Interrupt Controller uses 13 32-bit registers. These registers are located at an offset from MBAR of 0x0500. Register addresses are relative 
to this offset. Therefore, the actual register address is: 
MBAR + 0x0500 + register address
Hyperlinks to the Interrupt Controller registers are provided below:
7.2.4.1
ICTL Peripheral Interrupt Mask Register—MBAR + 0x0500
 
 (0x0500)
 
(0x0524)
(0x0504)
 (0x0528)
 
(0x0508)
(0x050C)
 (0x0530)
(0x0510)
 (0x0514)
 (0x0540)
 (0x0518)
 
 
(0x0544)
 (0x051C)
 
Table 7-4. ICTL Peripheral Interrupt Mask Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Per_mask
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Per_mask
Reserved
W
RESET:
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0