Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-14
Freescale Semiconductor
Interrupt Controller
7.2.4.9
ICTL Perstat, MainStat, MainStat, CritStat Encoded Register—MBAR + 0x0524
Table 7-12. ICTL PerStat, MainStat, CritStat Encoded Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
PSe
Reserved
MSe
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
CSe
Reserved
CEbSh
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:1
—
Reserved
2:7
PSe
Peripheral Status Encoded—makes a singular indication of the current peripheral interrupt
(6bits indicating 1 of 24 possible peripheral interrupts).
(6bits indicating 1 of 24 possible peripheral interrupts).
The msb operates as a flag bit and is set if any peripheral interrupt is currently being
presented by the Interrupt Controller (e.g., if peripheral interrupt source 0 is current, then this
register reads as 0x20). Normally it would not be necessary to clear this status register since
all peripheral interrupt sources are level sensitive.
presented by the Interrupt Controller (e.g., if peripheral interrupt source 0 is current, then this
register reads as 0x20). Normally it would not be necessary to clear this status register since
all peripheral interrupt sources are level sensitive.
Once an interrupt source negates at the input of the controller, the new input condition is
re-evaluated without software intervention. However, if ISR does not clear the interrupt
source (at the source module), then the controller is locked on the current interrupt and
cannot re-evaluate the input condition (possibly to detect the presence of a higher priority
interrupt). Therefore, ISR can force a re-evaluation of the input condition by writing 1 to the
msb of PSe. This sticky-bit clear operation is optional and can be used at the discretion of
the ISR writer.
re-evaluated without software intervention. However, if ISR does not clear the interrupt
source (at the source module), then the controller is locked on the current interrupt and
cannot re-evaluate the input condition (possibly to detect the presence of a higher priority
interrupt). Therefore, ISR can force a re-evaluation of the input condition by writing 1 to the
msb of PSe. This sticky-bit clear operation is optional and can be used at the discretion of
the ISR writer.
The encoded value cross-reference to a specific source is described in ICTL Peripheral
Interrupt Mask Register and re-stated in ICTL Peripheral Interrupt Status All Register. In all
cases, the peripheral status encoded value converts to a single source module (i.e., no
additional status parsing is required at the Interrupt Controller).
Interrupt Mask Register and re-stated in ICTL Peripheral Interrupt Status All Register. In all
cases, the peripheral status encoded value converts to a single source module (i.e., no
additional status parsing is required at the Interrupt Controller).
8:9
—
Reserved
10:15
MSe
Main Status Encoded—makes a singular indication of the current main interrupt (6 bits
indicating 1 of 17 possible main interrupts).
indicating 1 of 17 possible main interrupts).
The msb operates as a flag bit, as described above. The msb can also be written to 1 to force
a re-evaluation of the main interrupt sources.
a re-evaluation of the main interrupt sources.
The cross-reference of the encoded value to a particular source is described in Reg5 (main
mask) and re-stated in ICTL Main Status All Register.
mask) and re-stated in ICTL Main Status All Register.
All MSe values convert to a single source module, EXCEPT Main source 4 (LO_int), which
indicates a peripheral source is active. In this case it is necessary to parse the PSe to
determine which peripheral source is active. See Note
indicates a peripheral source is active. In this case it is necessary to parse the PSe to
determine which peripheral source is active. See Note
1
.
16:20
—
Reserved