Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-38
Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.1.6
GPS Simple GPIO Data Input Values Register —MBAR + 0x0B14
24:27
PSC2
Individual bits to control the state of pins configured as GPIO output.
bit 24 controls GPIO_PSC2_3 (PSC2_3 pin)
bit 25 controls GPIO_PSC2_2 (PSC2_2 pin)
bit 26 controls GPIO_PSC2_1 (PSC2_1 pin)
bit 27 controls GPIO_PSC2_0 (PSC2_0 pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
28:31
PSC1
Individual bits to control the state of pins configured as GPIO output.
bit 28 controls GPIO_PSC1_3 (PSC1_3 pin)
bit 29 controls GPIO_PSC1_2 (PSC1_2 pin)
bit 30 controls GPIO_PSC1_1 (PSC1_1 pin)
bit 31 controls GPIO_PSC1_0 (PSC1_0 pin)
0 = Drive 0 on the pin (default)
1 = Drive 1 on the pin
Table 7-26. GPS Simple GPIO Data Input Values Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
IRDA
ETHR
Reserved
USB
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
PSC3
PSC2
PSC1
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:1
—
Reserved
2:3
IRDA
Individual status bits reflecting the state of corresponding GPIO pins.
bit 2 reflects GPIO_IRDA_1 (IR_USB_CLK pin)
bit 3 reflects GPIO_IRDA_0 (IRDA_TX pin)
4:7
ETHR
Individual status bits reflecting the state of corresponding GPIO pins.
bit 4 reflects GPIO_ETHI_3 (ETH_11 pin)
bit 5 reflects GPIO_ETHI_2 (ETH_10 pin)
bit 6 reflects GPIO_ETHI_1 (ETH_9 pin)
bit 7 reflects GPIO_ETHI_0 (ETH_8 pin)
8:11
—
Reserved
Bit
Name
Description