Freescale Semiconductor MPC5200B ユーザーズマニュアル
Modes of Operation
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
9-7
In this mode, the peripheral address and data lines are limited to a total of 32 in Legacy Modes, to 40 or 48 in Large Flash or to 56 in MOST
Graphics mode. They are driven/read simultaneously on the external AD bus. A single dedicated R/W pin is driven to indicate read or write.
An individually dedicated CS pin is driven low while an external access is active.
Graphics mode. They are driven/read simultaneously on the external AD bus. A single dedicated R/W pin is driven to indicate read or write.
An individually dedicated CS pin is driven low while an external access is active.
Wait states are programmable and simply select how many PCI clocks the CS pin (and related signals) remain asserted. Separate values are
available for Read cycles versus Write Cycles. These values can be combined to create extremely long (up to 16 bits) Write cycles. Byte lane
swapping is separately programmable between Reads versus Writes and can be used to perform Endian conversions. The 24-bit data width is
not supported.
available for Read cycles versus Write Cycles. These values can be combined to create extremely long (up to 16 bits) Write cycles. Byte lane
swapping is separately programmable between Reads versus Writes and can be used to perform Endian conversions. The 24-bit data width is
not supported.
Peripherals can be marked as read-only or write-only by setting a control bit in the appropriate LPC register. Attempted accesses in violation
of this setting are prevented and result in either a Bus Error and/or an Interrupt as controlled by corresponding Enable bits. Each CS pin can
be individually enabled/disabled and the entire LPC module has a Master Enable bit. No software reset bit is provided or needed.
of this setting are prevented and result in either a Bus Error and/or an Interrupt as controlled by corresponding Enable bits. Each CS pin can
be individually enabled/disabled and the entire LPC module has a Master Enable bit. No software reset bit is provided or needed.
The non-multiplexed mode requires no external logic for interfacing to simple devices such as Flash ROM, E2PROM or SRAM. It is faster
than the multiplexed mode because data and address are provided in a single tenure. The supported address space is limited by the 26 address
lines.
than the multiplexed mode because data and address are provided in a single tenure. The supported address space is limited by the 26 address
lines.
9.4.2
MUXed Mode
In MUXed mode the addresses and data are multiplexed
using dual tenure. First, the address is put on the shared address/data
bus and ALE is asserted. Then the data is driven when the chip select is asserted.
Twelve different modes of address and
data sizes can be configured:
NOTE
The 24-bit data width is not supported.
The total supported Memory space consists of four banks.
Bank select bits are written in a register by the e300 processor. They can be used as individual selects or as encoded values. They are presented
on the bus during the address tenure as additional upper address bits.
on the bus during the address tenure as additional upper address bits.
In this mode, an address tenure is generated that can be up to 25bits of active address. The additional address bits drive:
•
a TSIZE value (3 bits)
•
a Bank Select value (2 bits)
An ALE signal is asserted (active lo) during this address tenure. ALE width is always one PCI bus clock. The dedicated R/W output is also
driven with ALE (and throughout the cycle). One clock afterALE negates, the appropriate CS pin asserts (low) and the AD bus enters the data
tenure. The CS pin and this data tenure remain active until the programmed wait states expire, or the peripheral responds with an ACK
assertion. ACK polarity is active low, but can be programmed to be ignored. The data tenure can contain up to the full 32-bit width. However,
the data width is programmable to support dynamically bus-sized transactions.
driven with ALE (and throughout the cycle). One clock afterALE negates, the appropriate CS pin asserts (low) and the AD bus enters the data
tenure. The CS pin and this data tenure remain active until the programmed wait states expire, or the peripheral responds with an ACK
assertion. ACK polarity is active low, but can be programmed to be ignored. The data tenure can contain up to the full 32-bit width. However,
the data width is programmable to support dynamically bus-sized transactions.
Table 9-4. MUXed Mode Options
Category
Address Size
Data Size
Memory Size
per Bank
Memory Size
Total
Comments
Legacy
8
8
256 Bytes
1 kBytes
Legacy
8
16
256 Bytes
1 kBytes
A0 not used.
Legacy
8
32
256 Bytes
1 kBytes
A0, A1 not used.
Legacy
16
8
64 kBytes
256 kBytes
Legacy
16
16
64 kBytes
256 kBytes
A0 not used.
Legacy
16
32
64 kBytes
256 kBytes
A0, A1 not used.
Legacy
24
8
16 MBytes
64 MBytes
Legacy
24
16
16 MBytes
64 MBytes
A0 not used.
Legacy
24
32
16 MBytes
64 MBytes
A0, A1 not used.
Legacy
25
8
32 MBytes
128 MBytes
Legacy
25
16
32 MBytes
128 MBytes
BOOT
Legacy
25
32
32 MBytes
128 MBytes
BOOT