Freescale Semiconductor MPC5200B ユーザーズマニュアル
Programmer’s Model
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
9-25
9.7.2.4
SCLPC Enable Register—MBAR + 0x3C0C
16:22
—
Reserved
23
DAI
Disable Auto Increment. Normally, SCLPC and LPC will present sequential
incrementing addresses to the peripheral as the Packet proceeds. If the peripheral is
operating as a single address Fifo, then the DAI bit should be set to 1. When set,
addresses to the peripheral will be stuck at Start_Address for every transaction.
incrementing addresses to the peripheral as the Packet proceeds. If the peripheral is
operating as a single address Fifo, then the DAI bit should be set to 1. When set,
addresses to the peripheral will be stuck at Start_Address for every transaction.
For DAI operation, the BPT field *MUST* be set to the port size of the peripheral.
24:27
—
Reserved
28:31
BPT
Bytes Per Transaction. Indicates number of bytes per transaction. The "only" valid
entries in this field are decimal/hex 1, 2, 4, or 8 bytes (i.e. binary 0001, 0010, 0100,
1000). BPT should not be set to less than the peripheral port size, but certainly can
be set to larger than the peripheral port size. The higher the BPT value, the greater
the throughput.
entries in this field are decimal/hex 1, 2, 4, or 8 bytes (i.e. binary 0001, 0010, 0100,
1000). BPT should not be set to less than the peripheral port size, but certainly can
be set to larger than the peripheral port size. The higher the BPT value, the greater
the throughput.
Note: Start_Address and Packet_Size values *must* be aligned/multiples of BPT.
For DAI operation, BPT must be set to the peripheral port size.
For DAI operation, BPT must be set to the peripheral port size.
Table 9-16. SCLPC Enable Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
RC
Reserved
RF
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
AIE
NIE
Reserved
ME
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:6
—
Reserved
7
RC
Reset Controller. This bit allows for a Software reset of the SCLPC state machine.
Writing a 1 to this bit will reset the SCLPC state machine. Reset will be maintained
as long as this bit is high. Software must write this bit low to release the reset and
start operation.
Writing a 1 to this bit will reset the SCLPC state machine. Reset will be maintained
as long as this bit is high. Software must write this bit low to release the reset and
start operation.
Note:
1.
Although RC does *not* reset this register interface, it does clear interrupt and
interrupt status conditions.
interrupt status conditions.
2.
Never reset the SCLPC Controller during a transaction (tx or rx).
8:14
—
Reserved
15
RF
Reset Fifo. This is the Fifo software reset bit. Writing a 1 to this bit will reset the
SCLPC Fifo. The Fifo must not be in reset for normal operation. Software reset of the
Fifo will clear the fifo of data, reset its read/write pointers, but *not* disturb previously
programmed Alarm and Granularity settings.
SCLPC Fifo. The Fifo must not be in reset for normal operation. Software reset of the
Fifo will clear the fifo of data, reset its read/write pointers, but *not* disturb previously
programmed Alarm and Granularity settings.
Note: Good Practice would be for software to set and clear the RC and RF bits prior
to programming and starting a Packet.
to programming and starting a Packet.
16:21
—
Reserved
Bits
Name
Description