Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-6
Freescale Semiconductor
Registers
10.3.1
PCI Controller Type 0 Configuration Space
MPC5200B supplies a type 0 PCI Configuration Space header. These registers are accessible as an offset from MBAR (
) or through externally mastered PCI Configuration Cycles.
NOTE
The internal PCI controller can discover itself (by means of connecting an AD line [preferably AD24
to AD31]to the PCI _IDSEL input). It is essential, when the PCI interface is used as a Target, to enable
the internal PCI controller to access via the external PCI bus its own PCI registers. This is the only
available way in order to clear any error flag RWC bit (Read/WriteClear bit).
to AD31]to the PCI _IDSEL input). It is essential, when the PCI interface is used as a Target, to enable
the internal PCI controller to access via the external PCI bus its own PCI registers. This is the only
available way in order to clear any error flag RWC bit (Read/WriteClear bit).
0x58
Reserved
...
0x7C
0x80
PCIRPSR
Rx Packet Size
0x84
PCIRSAR
Rx Start Address
0x88
PCIRTCR
Rx Transaction Control Register
0x8C
PCIRER
Rx Enables
0x90
PCIRNAR
Rx Next Address
0x94
PCIRLWR
Rx Last Word
0x98
PCIRDCR
Rx Bytes Done Counts
0x9C
PCIRSR
Rx Status
0xA0
PCIRPDCR
Rx Packets Done Counts
0xA4
Reserved
...
0xBC
0xC0
PCIRFDR
Rx FIFO Data
0xC4
PCIRFSR
Rx FIFO Status
0xC8
PCIRFCR
Rx FIFO Control
0xCC
PCIRFAR
Rx FIFO Alarm
0xD0
PCIRFRPR
Rx FIFO Read Pointer
0xD4
PCIRFWPR
Rx FIFO Write Pointer
0xD8
Reserved
...
0xFC
Reg
Addr
PCI
DWord
Offset
Reg
[31:24]
[23:16]
[15:8]
[7:0]
0x100
0x00
PCIIDR
Device ID
Vendor ID
0x104
0x01
PCISCR
Status
Command
Table 10-3. PCI Communication System Interface Register Map (continued)
Register
Offset
Mnemonic
Name