Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-12
Freescale Semiconductor
Registers
10.3.1.6
Base Address Register 1 PCIBAR1(RW) —MBAR + 0x0D14
10.3.1.7
CardBus CIS Pointer Register PCICCPR(RW) —MBAR + 0x0D28
This optional register contains the pointer to the Card Information Structure (CIS) for the CardBus card. All 32 bits of the register are
programmable by the Slave bus. It can only be read from the PCI Bus. Its reset value is 0x00000000.
programmable by the Slave bus. It can only be read from the PCI Bus. Its reset value is 0x00000000.
10.3.1.8
Subsystem ID/ Subsystem Vendor ID Registers PCISID(R)—MBAR + 0x0D2C
The Subsystem Vendor ID register contains the 16-bit manufacturer identification number of the add-in board or subsystem that contains this
PCI device. The Subsystem ID register contains the 16-bit subsystem identification number of the add-in board or subsystem that contains
this PCI device. A value of zero in these registers indicates there isn’t a Subsystem Vendor and Subsystem ID associated with the device. If
used, software must write to these registers before any PCI bus master reads them.
PCI device. The Subsystem ID register contains the 16-bit subsystem identification number of the add-in board or subsystem that contains
this PCI device. A value of zero in these registers indicates there isn’t a Subsystem Vendor and Subsystem ID associated with the device. If
used, software must write to these registers before any PCI bus master reads them.
All 32 bits of the register are programmable by the Slave bus. They can only be read from the PCI Bus. The reset value is 0x00000000.
10.3.1.9
Expansion ROM Base Address PCIERBAR(R) —MBAR + 0x0D30
Not implemented. Fixed to 0x00000000.
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Base
Address 1
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
pref
range
IO/M#
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bits
Name
Description
0:1
Base Address
Register 1
(BAR1)
MPC5200B PCI Base Address Register 1 (1Gbyte). Applies only when MPC5200B is
target. These bits are programmable (read/write from both the IP bus and PCI bus
Configuration cycles). This BAR register shall be used to point at the local SDRAM/DDR
Memory Space.
target. These bits are programmable (read/write from both the IP bus and PCI bus
Configuration cycles). This BAR register shall be used to point at the local SDRAM/DDR
Memory Space.
Note: The address ‘Window’ is much larger than the maximum theoretically supported
physical memory.
physical memory.
Note: This register should not point to the LocalPlus Memory Space. This is not supported.
2:27
Reserved
These bits are reserved.
28
prefetchable
access
(pref)
Fixed to 1. This bit indicates that the memory space defined by BAR1 is prefetchable.
Configuration software should write a 1 to this bit location.
Configuration software should write a 1 to this bit location.
29:30
range
Fixed to 00. This register indicates that base address 1 is 32 bits wide and can be mapped
anywhere in 32-bit address space. Configuration software should write 00 to these bit
locations.
anywhere in 32-bit address space. Configuration software should write 00 to these bit
locations.
31
IO or Memory
Space
(IO/M#)
Fixed to 0. This bit indicates that BAR1 is for memory space. Configuration software should
write a 0 to this bit location.
write a 0 to this bit location.
0 = Memory
1 = I/O