Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-46
Freescale Semiconductor
Functional Description
or more data phases. Data is transferred between initiator and target in each cycle that both IRDY and TRDY are asserted. Wait cycles may
be inserted in a data phase by the initiator (by negating IRDY) or by the target (by negating TRDY).
be inserted in a data phase by the initiator (by negating IRDY) or by the target (by negating TRDY).
Once an initiator has asserted IRDY, it cannot change IRDY or FRAME until the current data phase completes regardless of the state of TRDY.
Once a target has asserted TRDY or STOP, it cannot change DEVSEL,TRDY, or STOP until the current data phase completes. In simpler
terms, once an initiator or target has committed to the data transfer, it cannot back out.
Once a target has asserted TRDY or STOP, it cannot change DEVSEL,TRDY, or STOP until the current data phase completes. In simpler
terms, once an initiator or target has committed to the data transfer, it cannot back out.
When the initiator intends to complete only one more data transfer (which could be immediately after the address phase), FRAME is negated
and IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target indicates the final data transfer (by asserting TRDY),
the PCI bus may return to the idle state (both FRAME and IRDY are negated).
and IRDY is asserted (or kept asserted) indicating the initiator is ready. After the target indicates the final data transfer (by asserting TRDY),
the PCI bus may return to the idle state (both FRAME and IRDY are negated).
NOTE
No Fast Back-to-Back transactions are supported by the MPC5200B.
10.4.1.3
PCI Transactions
The figures in this section show the basic “memory read” and “memory write” command transactions.
shows a PCI burst read transaction (2-beat). The signal FRAME is driven low to initiate the transfer. Cycle 1 is the address phase
with valid address information driven on the AD bus and a PCI command driven on the C/BE bus. In cycle 2, the AD bus is in a turnaround
cycle because of the read on a muxed bus. The byte enables, which are active low, are driven onto the C/BE bus in this clock. Any combination
of byte enables can be asserted (none may be asserted). A target will respond to an address phase by driving the DEVSEL signal. The
specification allows for four types of decode operations. The target can drive DEVSEL in 1, 2 or 3 clocks depending on whether the target is
a fast, medium or slow decode device. A single device is allowed to drive DEVSEL should another agent fail to respond by the fourth clock.
This is called “subtractive decoding” in PCI terminology.
cycle because of the read on a muxed bus. The byte enables, which are active low, are driven onto the C/BE bus in this clock. Any combination
of byte enables can be asserted (none may be asserted). A target will respond to an address phase by driving the DEVSEL signal. The
specification allows for four types of decode operations. The target can drive DEVSEL in 1, 2 or 3 clocks depending on whether the target is
a fast, medium or slow decode device. A single device is allowed to drive DEVSEL should another agent fail to respond by the fourth clock.
This is called “subtractive decoding” in PCI terminology.
A valid transfer occurs when both IRDY and TRDY are asserted. If either are negated during a data phase, it is considered a wait state. The
target asserts a wait state in cycles 3 and 5 of
target asserts a wait state in cycles 3 and 5 of
. A master indicates that the final data phase is to occur by negating FRAME. The
final data phase occurs in cycle 6. Another agent cannot start an access until cycle 8.
Figure 10-2. PCI Read Terminated by Master
shows a write cycle which is terminated by the target. In this diagram the target responds as a slow device, driving DEVSEL in
cycle 4. The first data is transferred in cycle 4. The master inserts a wait state at cycle 5. The target indicates that it can accept only one more
transfer by asserting both TRDY and STOP at the same time in cycle 5. The signal STOP must remain asserted until FRAME negates. The
final data phase does not have to transfer data. If STOP and IRDY are both asserted while TRDY is negated, it is considered a target disconnect
without a transfer. See the PCI specification for more details.
transfer by asserting both TRDY and STOP at the same time in cycle 5. The signal STOP must remain asserted until FRAME negates. The
final data phase does not have to transfer data. If STOP and IRDY are both asserted while TRDY is negated, it is considered a target disconnect
without a transfer. See the PCI specification for more details.
CLK
FRAME
C/BE
IRDY
TRDY
DEVSEL
1
2
3
4
5
6
7
CMD
Address
Phase
Data Phase 1
Data Phase 2
Byte Enables
D1
A1
D2
8
AD
(wait)
(wait)