Freescale Semiconductor MPC5200B ユーザーズマニュアル

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Freescale Semiconductor

The address mapping in MPC5200B system is setup by software through a number of base address registers. (

 for more detail). The internal CPU writes the base address value to module base address register MBAR. MBAR holds the 

base address for the 256 Kbyte space allocated to internal registers. 

The MPC5200B-as-Target occupies 2 memory target address windows on the PCI bus. The location is determined by the values programmed 
to BAR0 and BAR1 of the PCI Type 00h Configuration space. These inbound memory window sizes are fixed to one 256 Kbyte window 
(BAR0) and one 1 Gbyte window (BAR1). 

PCI inbound address translation allows address translation to any space in the MPC5200B space (4 Gbyte of address space). The target base 
address translation registers TBATR0 and TBATR1 specify the location of the inbound memory window. These registers are described in 
Section 

. Address translation occurs for all enabled inbound transactions. If the enable bit of the 

Target Base Address Translation Registers is cleared, MPC5200B aborts all PCI memory transactions to that base address window. 

Note, the PCI configuring master can program BAR0 to overlap BAR1. The default address translation value is TBATR0 in that case. It is not 
recommended to program overlapping BAR0 and BAR1 or overlapping TBATR0 and TBATR1. An overlap of TBATRs can cause data 
write-over of BAR0 data.

The Initiator Window Base Address Registers are used to decode XL bus addresses for PCI bus transactions. The base address and base 
address mask values define the upper byte of address to decode. The XL bus address space in MPC5200B dedicated to PCI transactions can 
be mapped to two 16-Mbyte or larger address spaces in MPC5200B. In normal operation, software should not program either Target Address 
Window Translation Register to address Initiator Window space. In that event, MPC5200B-as-Target transaction would propagate through 
MPC5200B’s internal bus and request PCI bus access as the PCI Initiator. The PCI arbiter could see the PCI bus as busy (target read transaction 
in progress) and only a time-out would free the PCI bus.

Single-Beat 1 -> 4 byte Write

x

1

x

1

true

Special Cycle

1.

Dual Address Cycles and Memory Write and Invalidate Commands are not supported

2.

x means “don’t care”