Manualsbrain.com
  1. マニュアル
  2. ブランド
  3. Freescale Semiconductor
  4. MPC5200B
  5. ユーザーズマニュアル

Freescale Semiconductor MPC5200B ユーザーズマニュアル

ダウンロード
ページ / 762
ATA Register Interface
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
11-15
11.3.3.6
ATA Drive Sector Count Register—MBAR + 0x3A68
 
11.3.3.7
ATA Drive Sector Number Register—MBAR + 0x3A6C
 
Table 11-24. ATA Drive Sector Count Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Data
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:7
Data
Bit content is command dependent. For most read/write commands, this register indicates 
the total number of sectors requested for transfer.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and 
DMACK is not asserted. If register is written when BSY and DRQ bits are set to 1, the result 
is indeterminate.
Register content is not valid when drive is in sleep mode.
8:31
—
Reserved
Table 11-25. ATA Drive Sector Number Register
msb  0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Data
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:7
Data
Bit content is command dependent. For most commands, this register indicates the data 
transfer starting sector number for when CHS addressing is enabled. This register indicates 
part of the LBA address when the LBA addressing is enabled.
Register is written only when ATA drive status register bits BSY and DRQ equal 0 and 
DMACK is not asserted. If register is written when BSY and DRQ bits are set to 1, the result 
is indeterminate.
Register content is not valid when drive is in sleep mode.
8:31
—
Reserved