Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
11-22
Freescale Semiconductor
ATA Host Controller Operation
If ATA drive address space is accessed by CPU, the ATA IPBI module generates:
•
a signal to enable the PIO mode state machine
•
a wait state to the IPBI module to hold off any further IPBI module access
The PIO state machine indicates transfer is in progress to the IPBI module. This extends the transfer wait to the IPBI module until the PIO
transaction is complete.
transaction is complete.
11.4.2
DMA State Machine
The interface between the ATA Controller DMA channel and the rest of the system is through a standard Type 1 BestComm FIFO interface.
shows the timing requirements specified in the ATA-4 spec for multiword DMA data transfers.
11.4.2.1
Software Requirements
Software calculates the appropriate values of TD and TK based on information reported for the cycle time (T0) in the drive’s IDENTIFY
DEVICE data and the operating clock frequency. Cycle time (T0) must be greater than the sum of TD and TK.
DEVICE data and the operating clock frequency. Cycle time (T0) must be greater than the sum of TD and TK.
t9
3
N/A (Use t4 instead)
—
—
tA
t1
Check IORDY
IORDY=1
tB
N/A (Timing controlled by drive controller)
—
—
tC
N/A (Timing controlled by drive controller)
—
—
Note:
1.
Since t1 and t1
are both minimum specs, and t1 <= t1 for PIO modes 0–2, and t1 >= t1 for PIO modes 3–4, t1 is used
to count both, by loading in an initial value that depends on the PIO mode being used. This is the responsibility of
software.
software.
2.
Since t3 (WDATA setup time) is a minimum, and t3 <= t2 for all PIO modes, t2 is used to determine when to drive
Write_Data on DD.
Write_Data on DD.
3.
Since t4 and t9 are both minimum specs, and t4 >= t9 for all PIO modes, t4 is used to count from DIOR/DIOW negate
to CS[1]FX/CS[3]FX/ADDR negate.
to CS[1]FX/CS[3]FX/ADDR negate.
Table 11-32. Multiword DMA Timing Requirements
Counter
Start from
Activity at end
Dependencies
TM
START (Negate CS0, CS1,
set DMA_In_Progress flag)
set DMA_In_Progress flag)
Assert DMACK,
Assert DIOR/DIOW,
Write Data ready
DMARQ asserted by drive
TE
N/A (Timing controlled
by drive controller)
—
—
TD
TM
Negate DIOR/DIOW,
Latch Read Data/Drive Write Data
DMARQ=1
TK
TD
Assert DIOR/DIOW
DMARQ=1
TH
TD
Ready for new write data
DMARQ=1
T0
TD
Begin next cycle
DMARQ=1
Start TJ, Start TN
DMARQ=0
TJ
T0
Negate DMACK,
Go to Idle
DMARQ Negated,
DMACK asserted, T0=0
TN
T0
Clear DMA_In_Progress flag.
Allow CS0, CS1 to be driven
DMARQ Negated,
DMACK asserted, T0=0
Table 11-31. PIO Timing Requirements (continued)
Counter
Start from
Activity at end
Dependencies